ddr1_wr_data_fifo_16.vhd

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-------------------------------------------------------------------------------
-- Copyright (c) 2006 Xilinx, Inc.
-- This design is confidential and proprietary of Xilinx, All Rights Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /   Vendor: Xilinx
-- \   \   \/    Version: 1.1
--  \   \        Filename: ddr1_wr_data_fifo_16.vhd
--  /   /        Date Last Modified: 5/10/06
-- /___/   /\    Date Created:
-- \   \  /  \
--  \___\/\___\
-- 
--Device: Virtex-5
--Purpose: User Interface write FIFO (to memory)
--Reference:
--    XAPP851
--Revision History:
--    Rev 1.0 - Internal release. Author: Toshihiko Moriyama. 4/29/06.
--    Rev 1.1 - External release. Added header. Removed commented FIFO16
--              component. Substituted FIFO16 w/ FIFO36. 5/10/06.
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

library UNISIM;
use UNISIM.VCOMPONENTS.ALL;


entity ddr1_wr_data_fifo_16 is
port(
       clk0 			: in std_logic;
       clk90            : in std_logic;
       rst    			: in std_logic;
       --Write data fifo signals
       app_Wdf_data 	: in std_logic_vector(31 downto 0);
       app_mask_data    : in std_logic_vector(3 downto 0);
       app_Wdf_WrEn 	: in std_logic;
       ctrl_Wdf_RdEn 	: in std_logic;
       Wdf_data 		: out std_logic_vector(31 downto 0);
       mask_data        : out std_logic_vector(3 downto 0);
       wr_df_almost_full : out std_logic
       );
end ddr1_wr_data_fifo_16;

architecture arch of ddr1_wr_data_fifo_16 is

signal ctrl_Wdf_RdEn_270 : std_logic;
signal ctrl_Wdf_RdEn_90  : std_logic;


begin

process(clk0)
begin
--if clk90'event and clk90 = '0' then
if clk0'event and clk0 = '0' then
          ctrl_Wdf_RdEn_270 <= ctrl_Wdf_RdEn;
  end if;
end process;


--process(clk90)
process(clk0)
begin
--if clk90'event and clk90 = '1' then
if clk0'event and clk0 = '1' then
          ctrl_Wdf_RdEn_90 <= ctrl_Wdf_RdEn_270;
   end if;
end process;


Wdf_1 : FIFO36
generic map
(
ALMOST_FULL_OFFSET	    => X"0080",
ALMOST_EMPTY_OFFSET	    => X"0007",
DATA_WIDTH		        => 36,
DO_REG                  => 1,
EN_SYN                  => FALSE,
FIRST_WORD_FALL_THROUGH => TRUE
)
port map (
ALMOSTEMPTY       =>open,
ALMOSTFULL        => wr_df_almost_full,
DO                => Wdf_data(31 downto 0),
DOP               => mask_data(3 downto 0),
EMPTY             => open,
FULL              => open,
RDCOUNT           => open,
RDERR             => open,
WRCOUNT           => open,
WRERR             => open,
DI                => app_Wdf_data(31 downto 0),
DIP               => app_mask_data(3 downto 0),
--RDCLK             => clk90,
RDCLK             => clk0,
RDEN              => ctrl_Wdf_RdEn_90,
RST               => rst,
WRCLK             => clk0,
WREN              => app_Wdf_WrEn
);

end arch;