ddr1_rd_wr_addr_fifo.vhd

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-------------------------------------------------------------------------------
-- Copyright (c) 2006 Xilinx, Inc.
-- This design is confidential and proprietary of Xilinx, All Rights Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /   Vendor: Xilinx
-- \   \   \/    Version: 1.1
--  \   \        Filename: ddr1_rd_wr_addr_fifo.vhd
--  /   /        Date Last Modified: 5/10/06
-- /___/   /\    Date Created:
-- \   \  /  \
--  \___\/\___\
-- 
--Device: Virtex-5
--Purpose: User Interface command/address FIFO (aka Read/Write Address FIFO)
--Reference:
--    XAPP851
--Revision History:
--    Rev 1.0 - Internal release. Author: Toshihiko Moriyama. 4/29/06.
--    Rev 1.1 - External release. Added header. Removed commented FIFO16
--              component. Substituted FIFO16 w/ FIFO36. 5/10/06.
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;

library UNISIM;
use UNISIM.vcomponents.all;

use work.ddr1_parameters.all;

entity ddr1_rd_wr_addr_fifo is
	port( clk0         : in std_logic;
	      rst            : in std_logic;
	      app_af_addr    : in std_logic_vector(35 downto 0);
	      app_af_WrEn    : in std_logic;
	      ctrl_af_RdEn   : in std_logic;
	      af_addr        : out std_logic_vector(35 downto 0);
	      af_Empty       : out std_logic;
	      af_Almost_Full : out std_logic
	    );
end ddr1_rd_wr_addr_fifo;

architecture arch of ddr1_rd_wr_addr_fifo is

signal fifo_input_write_addr	: std_logic_vector(35 downto 0);
signal fifo_output_write_addr	: std_logic_vector(35 downto 0);
signal compare_value_r		: std_logic_vector(35 downto 0);
signal app_af_addr_r		: std_logic_vector(35 downto 0);
signal fifo_input_addr_r	: std_logic_vector(35 downto 0);
signal af_en_r			: std_logic;
signal af_en_2r			: std_logic;
signal compare_result		: std_logic;

begin

fifo_input_write_addr <= compare_result & app_af_addr_r(34 downto 0);
af_addr		      <= fifo_output_write_addr;
compare_result <= '0' when (compare_value_r((no_of_cs + bank_address + row_address + col_ap_width- 1) downto col_ap_width)
			= fifo_input_write_addr((no_of_cs + bank_address + row_address + col_ap_width- 1) downto col_ap_width)) else
		  '1';

process( clk0)
begin
if(clk0'event and clk0 = '1') then
 if(rst = '1') then
       compare_value_r      <= (others => '0');
       app_af_addr_r	    <= (others  => '0');
       fifo_input_addr_r    <= (others => '0');
       af_en_r              <= '0';
       af_en_2r             <= '0';
 else
   if(af_en_r = '1') then
       compare_value_r	 <= fifo_input_write_addr;
   end if;
   app_af_addr_r	 <= app_af_addr;
   fifo_input_addr_r <= fifo_input_write_addr;
   af_en_r		 <= app_af_WrEn;
   af_en_2r		 <= af_en_r;
 end if;
end if;
end process;


-- Read/Write Address FIFO

af_fifo36 : FIFO36
generic map
(
ALMOST_FULL_OFFSET              => X"000F",
ALMOST_EMPTY_OFFSET             => X"0007",
DATA_WIDTH                      => 36,
DO_REG                          => 1,
EN_SYN                          => FALSE,
FIRST_WORD_FALL_THROUGH         => TRUE
)
port map
(
ALMOSTEMPTY     => open,
ALMOSTFULL      => af_Almost_Full,
DO              => fifo_output_write_addr(31 downto 0),
DOP             => fifo_output_write_addr(35 downto 32),
EMPTY           => af_Empty,
FULL            => open,
RDCOUNT         => open,
RDERR           => open,
WRCOUNT         => open,
WRERR           => open,
DI              => fifo_input_addr_r(31 downto 0),
DIP             => fifo_input_addr_r(35 downto 32),
RDCLK           => clk0,
RDEN            => ctrl_af_RdEn,
RST             => rst,
WRCLK           => clk0,
WREN            => af_en_2r
);

end arch;