ddr1_top.vhd

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-------------------------------------------------------------------------------
-- Copyright (c) 2006 Xilinx, Inc.
-- This design is confidential and proprietary of Xilinx, All Rights Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /   Vendor: Xilinx
-- \   \   \/    Version: 1.1
--  \   \        Filename: ddr1_top.vhd
--  /   /        Date Last Modified: 5/11/06
-- /___/   /\    Date Created:
-- \   \  /  \
--  \___\/\___\
-- 
--Device: Virtex-5
--Purpose: Top-level for DDR1 SDRAM Controller. For a user integrating
--         the DDR1 controller into their own design, they would instantiate
--         this module in their own code (but would need to handle clock
--         generation, reset synchronization, and instantiation of a few I/O
--         buffers themselves)
--Reference:
--    XAPP851
--Revision History:
--    Rev 1.0 - Internal release. Author: Toshihiko Moriyama. 4/29/06.
--    Rev 1.1 - External release. Added header. Added RST90 support.
--              Changed CK to vector. Changed ctrl_ddr_cke to single bit.
--              5/11/06.
-------------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

library work;
--use work.pkg_ddr1_phy.all;
use work.ddr1_parameters.all;


entity ddr1_top is
port (
	rst				: in	std_logic;
    rst90           : in    std_logic;
	clk0			: in	std_logic;
	clk90			: in	std_logic;

	-- IO signals
	CKE				: out	std_logic;
	CK				: out	std_logic_vector(clk_width - 1 downto 0);
	AD				: out	std_logic_vector(row_address - 1 downto 0);
	BA				: out	std_logic_vector(bank_address - 1 downto 0);
	CS_n			: out	std_logic_vector(no_of_cs - 1 downto 0);
	RAS_n			: out	std_logic;
	CAS_n			: out	std_logic;
	WE_n			: out	std_logic;
	DM				: out	std_logic_vector(data_mask_width - 1 downto 0);
	DQ				: inout	std_logic_vector(data_width - 1 downto 0);
	DQS				: inout	std_logic_vector(data_strobe_width - 1 downto 0);

	-- UI
	app_Addr		: in	std_logic_vector(35 downto 0);
	app_AddrEn		: in	std_logic;
	app_WrData		: in	std_logic_vector(data_width*2 - 1 downto 0);
	app_DataMask	: in	std_logic_vector(data_mask_width*2 - 1 downto 0);
	app_DataEn		: in	std_logic;
	app_rd_data		: out	std_logic_vector(data_width*2 - 1 downto 0);
	app_rd_valid	: out	std_logic;

	app_addr_AF		: out	std_logic;	-- Address FIFIO almost full
	app_WrData_AF	: out	std_logic;	-- Write data FIFO almost full

	ctrl_rdy		: out	std_logic;
	phy_error		: out	std_logic
);
end ddr1_top;

architecture RTL of ddr1_top is

	component phy_top is
	port(
	rst				: in	std_logic;
	rst90           : in    std_logic;
	clk0			: in	std_logic;
	clk90			: in	std_logic;

	-- IO signals (memory interface)
	CKE				: out	std_logic;
	CK				: out	std_logic_vector(clk_width - 1 downto 0);
	AD				: out	std_logic_vector(row_address - 1 downto 0);
	BA				: out	std_logic_vector(bank_address - 1 downto 0);
	CS_n			: out	std_logic_vector(no_of_cs - 1 downto 0);
	RAS_n			: out	std_logic;
	CAS_n			: out	std_logic;
	WE_n			: out	std_logic;
	DM				: out	std_logic_vector(data_mask_width - 1 downto 0);
	DQ				: inout	std_logic_vector(data_width - 1 downto 0);
	DQS				: inout	std_logic_vector(data_strobe_width - 1 downto 0);

	-- UI
	phy_rdy			: out	std_logic;
	phy_error		: out	std_logic;

	phy_addr_in		: in	std_logic_vector(row_address - 1 downto 0);
	phy_bank_in		: in	std_logic_vector(bank_address - 1 downto 0);
	phy_cs_n_in		: in	std_logic_vector(no_of_cs - 1 downto 0);
	phy_ras_n_in	: in	std_logic;
	phy_cas_n_in	: in	std_logic;
	phy_we_n_in		: in	std_logic;

	phy_wr_data_in	: in	std_logic_vector(data_width*2 - 1 downto 0);	-- Input write data with write command
	phy_wr_en_in	: in	std_logic;
	phy_wr_dm_in	: in	std_logic_vector(data_mask_width*2 - 1 downto 0);
	phy_rd_data_o	: out	std_logic_vector(data_width*2 - 1 downto 0);
	phy_rd_valid_o	: out	std_logic
	);
	end component;

	component ddr1_backend_fifos is
	port(
	clk0			: in std_logic;
	clk90			: in std_logic;
	rst				: in std_logic;
	app_af_addr		: in std_logic_vector(35 downto 0);
	app_af_WrEn		: in std_logic;
	ctrl_af_RdEn	: in std_logic;
	af_addr			: out std_logic_vector(35 downto 0);
	af_Empty		: out std_logic;
	af_Almost_Full	: out std_logic;
	app_Wdf_data	: in std_logic_vector((data_width*2 - 1) downto 0);
	app_mask_data	: in std_logic_vector((data_mask_width*2 - 1) downto 0);
	app_Wdf_WrEn	: in std_logic;
	ctrl_Wdf_RdEn	: in std_logic;
	Wdf_data		: out std_logic_vector((data_width*2 - 1) downto 0);
	mask_data		: out std_logic_vector((data_mask_width*2 - 1) downto 0);
	Wdf_Almost_Full	: out std_logic
	);
	end component;

	component ddr1_controller is
	port (
	clk0				: in	std_logic;
	refresh_clk			: in	std_logic;
	rst					: in	std_logic;
	af_addr				: in	std_logic_vector(35 downto 0);
	af_empty			: in	std_logic;
	burst_length		: out	std_logic_vector(2 downto 0);

	ctrl_af_RdEn		: out	std_logic;
	ctrl_Wdf_RdEn		: out	std_logic;
	ctrl_Dqs_Rst		: out	std_logic;
	ctrl_Dqs_En			: out	std_logic;
	ctrl_WrEn			: out	std_logic;
	ctrl_RdEn			: out	std_logic;
	ctrl_ddr_address	: out	std_logic_vector(row_address - 1 downto 0);
	ctrl_ddr_ba			: out	std_logic_vector(bank_address - 1 downto 0);
	ctrl_ddr_ras_L		: out	std_logic;
	ctrl_ddr_cas_L		: out	std_logic;
	ctrl_ddr_we_L		: out	std_logic;
	ctrl_ddr_cs_L		: out	std_logic_vector(no_of_cs - 1 downto 0);
	ctrl_ddr_cke		: out	std_logic;
	phy_Dly_Slct_Done	: in	std_logic
	);
	end component;

--	signal burst_length			: std_logic_vector(2 downto 0);

	signal ctrl_AddrRd			: std_logic;
	signal Addr					: std_logic_vector(35 downto 0);
	signal Addr_Empty			: std_logic;
	signal Addr_Almost_Full		: std_logic;
	signal ctrl_DataRd			: std_logic;
	signal WrData				: std_logic_vector(data_width*2 - 1 downto 0);
	signal DataMask				: std_logic_vector(data_mask_width*2 - 1 downto 0);
	signal Data_Almost_Full		: std_logic;

	signal phy_addr_in			: std_logic_vector(row_address - 1 downto 0);
	signal phy_bank_in			: std_logic_vector(bank_address - 1 downto 0);
	signal phy_cs_n_in			: std_logic_vector(no_of_cs - 1 downto 0);
	signal phy_ras_n_in			: std_logic;
	signal phy_cas_n_in			: std_logic;
	signal phy_we_n_in			: std_logic;
	signal phy_rdy				: std_logic;

	signal phy_wr_data_in		: std_logic_vector(data_width*2 - 1 downto 0);
	signal phy_wr_dm_in			: std_logic_vector(data_mask_width*2 - 1 downto 0);
	signal phy_wr_en_in			: std_logic;
	signal phy_rd_data_o		: std_logic_vector(data_width*2 - 1 downto 0);
	signal phy_rd_valid_o		: std_logic;

begin

--	burst_length <= BASE_MODE_REG(2 downto 0);

	ctrl_rdy <= phy_rdy;
	app_Addr_AF <= Addr_Almost_Full;
	app_WrData_AF <= Data_Almost_Full;


	BACKEND_FIFO_I : ddr1_backend_fifos
	port map (
	clk0			=> clk0,
	clk90			=> clk90,
	rst				=> rst,
	app_af_addr		=> app_Addr,
	app_af_WrEn		=> app_AddrEn,
	ctrl_af_RdEn	=> ctrl_AddrRd,
	af_addr			=> Addr,
	af_Empty		=> Addr_Empty,
	af_Almost_Full	=> Addr_Almost_Full,

	app_Wdf_data	=> app_WrData,
	app_mask_data	=> app_DataMask,
	app_Wdf_WrEn	=> app_DataEn,
	ctrl_Wdf_RdEn	=> ctrl_DataRd,
	Wdf_data		=> WrData,
	mask_data		=> DataMask,
	Wdf_Almost_Full	=> Data_Almost_Full
	);

	DDR1_CTRL_I : ddr1_controller
	port map (
	clk0				=> clk0,
	refresh_clk			=> clk0,
	rst					=> rst,
	af_addr				=> Addr,
	af_empty			=> Addr_Empty,
	burst_length		=> open,

	ctrl_af_RdEn		=> ctrl_AddrRd,
	ctrl_Wdf_RdEn		=> ctrl_DataRd,
	ctrl_Dqs_Rst		=> open,
	ctrl_Dqs_En			=> open,
	ctrl_WrEn			=> phy_wr_en_in,
	ctrl_RdEn			=> open,
	ctrl_ddr_address	=> phy_addr_in,
	ctrl_ddr_ba			=> phy_bank_in,
	ctrl_ddr_ras_L		=> phy_ras_n_in,
	ctrl_ddr_cas_L		=> phy_cas_n_in,
	ctrl_ddr_we_L		=> phy_we_n_in,
	ctrl_ddr_cs_L		=> phy_cs_n_in,
	ctrl_ddr_cke		=> open,
	phy_Dly_Slct_Done	=> phy_rdy
	);

	phy_wr_data_in	<= WrData;
	phy_wr_dm_in	<= DataMask;
	app_rd_data		<= phy_rd_data_o;
	app_rd_valid	<= phy_rd_valid_o;

	PHY_TOP_I : phy_top
	port map (
        rst			=> rst,
	rst90                   => rst90,
        clk0			=> clk0,
	clk90			=> clk90,

	CKE				=> CKE,
	CK				=> CK,
	AD				=> AD,
	BA				=> BA,
	CS_n			=> CS_n,
	RAS_n			=> RAS_n,
	CAS_n			=> CAS_n,
	WE_n			=> WE_n,
	DM				=> DM,
	DQ				=> DQ,
	DQS				=> DQS,

	-- UI
	phy_rdy			=> phy_rdy,
	phy_error		=> phy_error,

	phy_addr_in		=> phy_addr_in,
	phy_bank_in		=> phy_bank_in,
	phy_cs_n_in		=> phy_cs_n_in,
	phy_ras_n_in	=> phy_ras_n_in,
	phy_cas_n_in	=> phy_cas_n_in,
	phy_we_n_in		=> phy_we_n_in,

	phy_wr_data_in	=> phy_wr_data_in,
	phy_wr_en_in	=> phy_wr_en_in,
	phy_wr_dm_in	=> phy_wr_dm_in,
	phy_rd_data_o	=> phy_rd_data_o,
	phy_rd_valid_o	=> phy_rd_valid_o
	);

end RTL;