phy_adr_out.vhd

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-------------------------------------------------------------------------------
-- Copyright (c) 2006 Xilinx, Inc.
-- This design is confidential and proprietary of Xilinx, All Rights Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /   Vendor: Xilinx
-- \   \   \/    Version: 1.1
--  \   \        Filename: phy_adr_out.vhd
--  /   /        Date Last Modified: 5/10/06
-- /___/   /\    Date Created:
-- \   \  /  \
--  \___\/\___\
-- 
--Device: Virtex-5
--Purpose: Address and bank select output IOB flops
--Reference:
--    XAPP851
--Revision History:
--    Rev 1.0 - Internal release. Author: Toshihiko Moriyama. 4/29/06.
--    Rev 1.1 - External release. Added header. 5/10/06.
-------------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

library unisim ;
use unisim.vcomponents.all;

library work;
use work.ddr1_parameters.all;

entity phy_adr_out is
port(

	rst		: in	std_logic;
	clk0	: in	std_logic;

	-- internal interface
	addr_in	: in	std_logic_vector(row_address - 1 downto 0);
	bank_in	: in	std_logic_vector(bank_address - 1 downto 0);

	-- Memory interface
	AD		: out	std_logic_vector(row_address - 1 downto 0);
	BA		: out	std_logic_vector(bank_address - 1 downto 0)

);
end phy_adr_out;

-----------------------------------------------
architecture rtl of phy_adr_out is

	signal LOGIC_0		: std_logic;
	signal LOGIC_1		: std_logic;

	attribute iob		: string;

begin

	LOGIC_0	<= '0';
	LOGIC_1 <= '1';

	G_AD : for I in 0 to row_address - 1 generate
		attribute iob of AD_IOBFF	: label is "true";
	begin

	AD_IOBFF : FDCPE
	port map (
	Q	=> AD(I),
	C	=> clk0,
	CE	=> LOGIC_1,
	D	=> addr_in(I),
	CLR	=> LOGIC_0,
	PRE	=> rst
	);

	end generate;

	G_BA : for I in 0 to bank_address - 1 generate
		attribute iob of BA_IOBFF	: label is "true";
	begin

	BA_IOBFF : FDCPE
	port map (
	Q	=> BA(I),
	C	=> clk0,
	CE	=> LOGIC_1,
	D	=> bank_in(I),
	CLR	=> LOGIC_0,
	PRE	=> rst
	);

	end generate;

end rtl;