dec2.vhd

来自「基于ALTERA的cyclone 系列的控制电机的实验例程」· VHDL 代码 · 共 27 行

LIBRARY IEEE ;
 USE IEEE.STD_LOGIC_1164.ALL ;
  ENTITY Dec2 IS
    PORT ( CLK : IN STD_LOGIC;
           A  : IN  STD_LOGIC_VECTOR(1 DOWNTO 0) ;
           D  : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)  ) ;
 END ;
 ARCHITECTURE one OF Dec2 IS
 SIGNAL CQ : STD_LOGIC_VECTOR(1 DOWNTO 0);
 BEGIN
   PROCESS( CQ )
    BEGIN
        CASE  CQ  IS
          WHEN "00" =>  D <= "1001" ; 
          WHEN "01" =>  D <= "1100" ; 
          WHEN "10" =>  D <= "0110" ; 
          WHEN "11" =>  D <= "0011" ; 
          WHEN OTHERS =>  NULL ;
        END CASE ;
    END PROCESS ;
 PROCESS(CLK)
    BEGIN
       IF CLK'EVENT AND CLK = '1' THEN CQ <= A; END IF;
    END PROCESS;
END ;