四输入与非门电路.txt

VHDl编写的四输入与非门电路

四输入与非门电路
  法一：
library ieee;
use ieee.std_logic_1164.all;
entity nand4 is
   port(a,b,c,d:in std_logic;
              y:out std_logic;
end nand4;
   
architecture nand4_1 of nand4 is
  begin
  y<=not(a and band c and d);
end nand4_1;

   法二：
library ieee;
use ieee.std_logic_1164.all
    
entity nand4 is
  port(a.b,c,d:in std_logic;
             y:out std_logic);
end nand4;

architecture nand4_2 of nand4 si
  begin 
  p1:process(a,b,c,d)
   variable tmp:std_logic_vector(3 downto 0);
begin
   tmp:=a&b&c&d;
case tmp is
     when"0000"=>y<='1';
     when"0001"=>y<='1';
     when"0010"=>y<='1';
     when"0011"=>y<='1';
     when"0100"=>y<='1';
     when"0101"=>y<='1';
     when"0110"=>y<='1';
     when"0111"=>y<='1';
     when"1000"=>y<='1';
     when"1001"=>y<='1';
     when"1010"=>y<='1';
     when"1011"=>y<='1';
     when"1100"=>y<='1';
     when"1101"=>y<='1';
     when"1110"=>y<='1';
     when"1111"=>y<='1';
     when others=>y<='x';
end case;
end process;
end nand4_2;

   法二：
library ieee;
use ieee.std_logic_1164.all;

entity nand4 is
  port(a,b,c,d:in std_logic;
             y:out std_logic);
end nand4;
architecuture nand4_3 of nand4 is
component nand2
port(a,b:in std_logic;
       y:out std_logic);
end component;
component or2
port(a,b:in std_logic;
       y:out std_logic);
end component;
signal yy1,yy2:std_logic:
  begin
   u1:nand2 port map(a,b,yy1);
   u2:nand2 port map(c,d,yy2);
   u3:or2 port map (yy1,yy2,y);
end nand4_3;