top_level_timesim.vhd

8 Channel Digital Volt Meter

  signal dvm_N5445_MC_D2_PT_3 : STD_LOGIC; 
  signal dvm_N5445_MC_D2_PT_4 : STD_LOGIC; 
  signal dvm_N5445_MC_D2_PT_5 : STD_LOGIC; 
  signal dvm_N5445_MC_D2 : STD_LOGIC; 
  signal dvm_N5446_MC_Q : STD_LOGIC; 
  signal dvm_N5446_MC_D : STD_LOGIC; 
  signal dvm_N5446_MC_D1 : STD_LOGIC; 
  signal dvm_N5446_MC_D2_PT_0 : STD_LOGIC; 
  signal dvm_N5447 : STD_LOGIC; 
  signal dvm_N5446_MC_D2_PT_1 : STD_LOGIC; 
  signal dvm_N5446_MC_D2_PT_2 : STD_LOGIC; 
  signal dvm_N5446_MC_D2_PT_3 : STD_LOGIC; 
  signal dvm_N5446_MC_D2_PT_4 : STD_LOGIC; 
  signal dvm_N5446_MC_D2_PT_5 : STD_LOGIC; 
  signal dvm_N5446_MC_D2_PT_6 : STD_LOGIC; 
  signal dvm_N5446_MC_D2 : STD_LOGIC; 
  signal dvm_N5447_MC_Q : STD_LOGIC; 
  signal dvm_N5447_MC_D : STD_LOGIC; 
  signal dvm_N5447_MC_D1 : STD_LOGIC; 
  signal dvm_N5447_MC_D2_PT_0 : STD_LOGIC; 
  signal dvm_N5448 : STD_LOGIC; 
  signal dvm_N5447_MC_D2_PT_1 : STD_LOGIC; 
  signal dvm_N5447_MC_D2_PT_2 : STD_LOGIC; 
  signal dvm_N5447_MC_D2_PT_3 : STD_LOGIC; 
  signal dvm_N5447_MC_D2_PT_4 : STD_LOGIC; 
  signal dvm_N5447_MC_D2_PT_5 : STD_LOGIC; 
  signal dvm_N5447_MC_D2_PT_6 : STD_LOGIC; 
  signal dvm_N5447_MC_D2_PT_7 : STD_LOGIC; 
  signal dvm_N5447_MC_D2_PT_8 : STD_LOGIC; 
  signal dvm_N5447_MC_D2 : STD_LOGIC; 
  signal dvm_N5448_MC_Q : STD_LOGIC; 
  signal dvm_N5448_MC_D : STD_LOGIC; 
  signal dvm_N5448_MC_D1 : STD_LOGIC; 
  signal dvm_N5448_MC_D2_PT_0 : STD_LOGIC; 
  signal dvm_N5449 : STD_LOGIC; 
  signal dvm_N5448_MC_D2_PT_1 : STD_LOGIC; 
  signal dvm_N5448_MC_D2_PT_2 : STD_LOGIC; 
  signal dvm_N5448_MC_D2_PT_3 : STD_LOGIC; 
  signal dvm_N5448_MC_D2_PT_4 : STD_LOGIC; 
  signal dvm_N5448_MC_D2_PT_5 : STD_LOGIC; 
  signal dvm_N5448_MC_D2_PT_6 : STD_LOGIC; 
  signal dvm_N5448_MC_D2_PT_7 : STD_LOGIC; 
  signal dvm_N5448_MC_D2_PT_8 : STD_LOGIC; 
  signal dvm_N5448_MC_D2_PT_9 : STD_LOGIC; 
  signal dvm_N5448_MC_D2 : STD_LOGIC; 
  signal dvm_N5449_MC_Q : STD_LOGIC; 
  signal dvm_N5449_MC_D : STD_LOGIC; 
  signal dvm_N5449_MC_D1 : STD_LOGIC; 
  signal dvm_N5449_MC_D2_PT_0 : STD_LOGIC; 
  signal dvm_N5449_MC_D2_PT_1 : STD_LOGIC; 
  signal dvm_N5449_MC_D2_PT_2 : STD_LOGIC; 
  signal dvm_N5449_MC_D2_PT_3 : STD_LOGIC; 
  signal dvm_N5449_MC_D2_PT_4 : STD_LOGIC; 
  signal dvm_N5449_MC_D2_PT_5 : STD_LOGIC; 
  signal dvm_N5449_MC_D2_PT_6 : STD_LOGIC; 
  signal dvm_N5449_MC_D2_PT_7 : STD_LOGIC; 
  signal dvm_N5449_MC_D2_PT_8 : STD_LOGIC; 
  signal dvm_N5449_MC_D2_PT_9 : STD_LOGIC; 
  signal dvm_N5449_MC_D2 : STD_LOGIC; 
  signal dvm_wr_reg_num_0_MC_Q : STD_LOGIC; 
  signal dvm_wr_reg_num_0_MC_R_OR_PRLD : STD_LOGIC; 
  signal dvm_wr_reg_num_0_MC_D : STD_LOGIC; 
  signal dvm_wr_reg_num_0_MC_D1 : STD_LOGIC; 
  signal dvm_wr_reg_num_0_MC_D2_PT_0 : STD_LOGIC; 
  signal dvm_wr_reg_num_0_MC_D2_PT_1 : STD_LOGIC; 
  signal dvm_wr_reg_num_0_MC_D2_PT_2 : STD_LOGIC; 
  signal dvm_wr_reg_num_0_MC_D2_PT_3 : STD_LOGIC; 
  signal dvm_wr_reg_num_0_MC_D2_PT_4 : STD_LOGIC; 
  signal dvm_wr_reg_num_0_MC_D2 : STD_LOGIC; 
  signal dvm_wr_reg_num_1_MC_Q : STD_LOGIC; 
  signal dvm_wr_reg_num_1_MC_R_OR_PRLD : STD_LOGIC; 
  signal dvm_wr_reg_num_1_MC_D : STD_LOGIC; 
  signal dvm_wr_reg_num_1_MC_D1 : STD_LOGIC; 
  signal dvm_wr_reg_num_1_MC_D2_PT_0 : STD_LOGIC; 
  signal dvm_wr_reg_num_1_MC_D2_PT_1 : STD_LOGIC; 
  signal dvm_wr_reg_num_1_MC_D2_PT_2 : STD_LOGIC; 
  signal dvm_wr_reg_num_1_MC_D2_PT_3 : STD_LOGIC; 
  signal dvm_wr_reg_num_1_MC_D2_PT_4 : STD_LOGIC; 
  signal dvm_wr_reg_num_1_MC_D2 : STD_LOGIC; 
  signal dvm_wr_reg_num_2_MC_Q : STD_LOGIC; 
  signal dvm_wr_reg_num_2_MC_R_OR_PRLD : STD_LOGIC; 
  signal dvm_wr_reg_num_2_MC_D : STD_LOGIC; 
  signal dvm_wr_reg_num_2_MC_D1 : STD_LOGIC; 
  signal dvm_wr_reg_num_2_MC_D2_PT_0 : STD_LOGIC; 
  signal dvm_wr_reg_num_2_MC_D2_PT_1 : STD_LOGIC; 
  signal dvm_wr_reg_num_2_MC_D2_PT_2 : STD_LOGIC; 
  signal dvm_wr_reg_num_2_MC_D2_PT_3 : STD_LOGIC; 
  signal dvm_wr_reg_num_2_MC_D2 : STD_LOGIC; 
  signal flash_cs0n_MC_Q : STD_LOGIC; 
  signal flash_cs0n_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal flash_cs0n_MC_D : STD_LOGIC; 
  signal flash_cs0n_MC_D1 : STD_LOGIC; 
  signal flash_cs0n_MC_D2 : STD_LOGIC; 
  signal flash_wr_protect_MC_Q : STD_LOGIC; 
  signal flash_wr_protect_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal flash_wr_protect_MC_D : STD_LOGIC; 
  signal flash_wr_protect_MC_D1 : STD_LOGIC; 
  signal flash_wr_protect_MC_D2 : STD_LOGIC; 
  signal io13_MC_Q : STD_LOGIC; 
  signal io13_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal io13_MC_D : STD_LOGIC; 
  signal io13_MC_D1 : STD_LOGIC; 
  signal io13_MC_D2_PT_0 : STD_LOGIC; 
  signal io13_MC_D2_PT_1 : STD_LOGIC; 
  signal io13_MC_D2_PT_2 : STD_LOGIC; 
  signal io13_MC_D2 : STD_LOGIC; 
  signal led1_sel_MC_Q : STD_LOGIC; 
  signal led1_sel_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal led1_sel_MC_D : STD_LOGIC; 
  signal led1_sel_MC_D1 : STD_LOGIC; 
  signal led1_sel_MC_D2 : STD_LOGIC; 
  signal led2_sel_MC_Q : STD_LOGIC; 
  signal led2_sel_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal led2_sel_MC_D : STD_LOGIC; 
  signal led2_sel_MC_D1 : STD_LOGIC; 
  signal led2_sel_MC_D2 : STD_LOGIC; 
  signal led3_sel_MC_Q : STD_LOGIC; 
  signal led3_sel_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal led3_sel_MC_D : STD_LOGIC; 
  signal led3_sel_MC_D1 : STD_LOGIC; 
  signal led3_sel_MC_D2 : STD_LOGIC; 
  signal led4_sel_MC_Q : STD_LOGIC; 
  signal led4_sel_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal led4_sel_MC_D : STD_LOGIC; 
  signal led4_sel_MC_D1 : STD_LOGIC; 
  signal led4_sel_MC_D2 : STD_LOGIC; 
  signal oen_MC_Q : STD_LOGIC; 
  signal oen_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal oen_MC_D : STD_LOGIC; 
  signal oen_MC_D1_PT_0 : STD_LOGIC; 
  signal oen_MC_D1 : STD_LOGIC; 
  signal oen_MC_D2 : STD_LOGIC; 
  signal osc_cntrl_MC_Q : STD_LOGIC; 
  signal osc_cntrl_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal osc_cntrl_MC_D : STD_LOGIC; 
  signal osc_cntrl_MC_D1 : STD_LOGIC; 
  signal osc_cntrl_MC_D2 : STD_LOGIC; 
  signal reset_memn_MC_Q : STD_LOGIC; 
  signal reset_memn_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal reset_memn_MC_D : STD_LOGIC; 
  signal reset_memn_MC_D1 : STD_LOGIC; 
  signal reset_memn_MC_D2 : STD_LOGIC; 
  signal rise_fall_MC_Q : STD_LOGIC; 
  signal rise_fall_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal rise_fall_MC_D : STD_LOGIC; 
  signal rise_fall_MC_D1 : STD_LOGIC; 
  signal rise_fall_MC_D2 : STD_LOGIC; 
  signal rwn_MC_Q : STD_LOGIC; 
  signal rwn_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal rwn_MC_D : STD_LOGIC; 
  signal rwn_MC_D1 : STD_LOGIC; 
  signal rwn_MC_D2_PT_0 : STD_LOGIC; 
  signal rwn_MC_D2_PT_1 : STD_LOGIC; 
  signal rwn_MC_D2_PT_2 : STD_LOGIC; 
  signal rwn_MC_D2 : STD_LOGIC; 
  signal sp_a_0_MC_Q : STD_LOGIC; 
  signal sp_a_0_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal sp_a_0_MC_D : STD_LOGIC; 
  signal sp_a_0_MC_D1 : STD_LOGIC; 
  signal sp_a_0_MC_D2 : STD_LOGIC; 
  signal sp_d_0_MC_Q : STD_LOGIC; 
  signal sp_d_0_MC_OE : STD_LOGIC; 
  signal sp_d_0_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal sp_d_0_MC_D : STD_LOGIC; 
  signal d_0_II_UIM : STD_LOGIC; 
  signal sp_d_0_MC_D1_PT_0 : STD_LOGIC; 
  signal sp_d_0_MC_D1 : STD_LOGIC; 
  signal sp_d_0_MC_D2 : STD_LOGIC; 
  signal sp_d_0_MC_BUFOE_OUT : STD_LOGIC; 
  signal sp_d_10_MC_Q : STD_LOGIC; 
  signal sp_d_10_MC_OE : STD_LOGIC; 
  signal sp_d_10_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal sp_d_10_MC_D : STD_LOGIC; 
  signal d_10_II_UIM : STD_LOGIC; 
  signal sp_d_10_MC_D1_PT_0 : STD_LOGIC; 
  signal sp_d_10_MC_D1 : STD_LOGIC; 
  signal sp_d_10_MC_D2 : STD_LOGIC; 
  signal sp_d_10_MC_BUFOE_OUT : STD_LOGIC; 
  signal sp_d_11_MC_Q : STD_LOGIC; 
  signal sp_d_11_MC_OE : STD_LOGIC; 
  signal sp_d_11_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal sp_d_11_MC_D : STD_LOGIC; 
  signal d_11_II_UIM : STD_LOGIC; 
  signal sp_d_11_MC_D1_PT_0 : STD_LOGIC; 
  signal sp_d_11_MC_D1 : STD_LOGIC; 
  signal sp_d_11_MC_D2 : STD_LOGIC; 
  signal sp_d_11_MC_BUFOE_OUT : STD_LOGIC; 
  signal sp_d_12_MC_Q : STD_LOGIC; 
  signal sp_d_12_MC_OE : STD_LOGIC; 
  signal sp_d_12_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal sp_d_12_MC_D : STD_LOGIC; 
  signal d_12_II_UIM : STD_LOGIC; 
  signal sp_d_12_MC_D1_PT_0 : STD_LOGIC; 
  signal sp_d_12_MC_D1 : STD_LOGIC; 
  signal sp_d_12_MC_D2 : STD_LOGIC; 
  signal sp_d_12_MC_BUFOE_OUT : STD_LOGIC; 
  signal sp_d_13_MC_Q : STD_LOGIC; 
  signal sp_d_13_MC_OE : STD_LOGIC; 
  signal sp_d_13_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal sp_d_13_MC_D : STD_LOGIC; 
  signal d_13_II_UIM : STD_LOGIC; 
  signal sp_d_13_MC_D1_PT_0 : STD_LOGIC; 
  signal sp_d_13_MC_D1 : STD_LOGIC; 
  signal sp_d_13_MC_D2 : STD_LOGIC; 
  signal sp_d_13_MC_BUFOE_OUT : STD_LOGIC; 
  signal sp_d_14_MC_Q : STD_LOGIC; 
  signal sp_d_14_MC_OE : STD_LOGIC; 
  signal sp_d_14_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal sp_d_14_MC_D : STD_LOGIC; 
  signal d_14_II_UIM : STD_LOGIC; 
  signal sp_d_14_MC_D1_PT_0 : STD_LOGIC; 
  signal sp_d_14_MC_D1 : STD_LOGIC; 
  signal sp_d_14_MC_D2 : STD_LOGIC; 
  signal sp_d_14_MC_BUFOE_OUT : STD_LOGIC; 
  signal sp_d_15_MC_Q : STD_LOGIC; 
  signal sp_d_15_MC_OE : STD_LOGIC; 
  signal sp_d_15_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal sp_d_15_MC_D : STD_LOGIC; 
  signal d_15_II_UIM : STD_LOGIC; 
  signal sp_d_15_MC_D1_PT_0 : STD_LOGIC; 
  signal sp_d_15_MC_D1 : STD_LOGIC; 
  signal sp_d_15_MC_D2 : STD_LOGIC; 
  signal sp_d_15_MC_BUFOE_OUT : STD_LOGIC; 
  signal sp_d_1_MC_Q : STD_LOGIC; 
  signal sp_d_1_MC_OE : STD_LOGIC; 
  signal sp_d_1_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal sp_d_1_MC_D : STD_LOGIC; 
  signal d_1_II_UIM : STD_LOGIC; 
  signal sp_d_1_MC_D1_PT_0 : STD_LOGIC; 
  signal sp_d_1_MC_D1 : STD_LOGIC; 
  signal sp_d_1_MC_D2 : STD_LOGIC; 
  signal sp_d_1_MC_BUFOE_OUT : STD_LOGIC; 
  signal sp_d_2_MC_Q : STD_LOGIC; 
  signal sp_d_2_MC_OE : STD_LOGIC; 
  signal sp_d_2_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal sp_d_2_MC_D : STD_LOGIC; 
  signal d_2_II_UIM : STD_LOGIC; 
  signal sp_d_2_MC_D1_PT_0 : STD_LOGIC; 
  signal sp_d_2_MC_D1 : STD_LOGIC; 
  signal sp_d_2_MC_D2 : STD_LOGIC; 
  signal sp_d_2_MC_BUFOE_OUT : STD_LOGIC; 
  signal sp_d_3_MC_Q : STD_LOGIC; 
  signal sp_d_3_MC_OE : STD_LOGIC; 
  signal sp_d_3_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal sp_d_3_MC_D : STD_LOGIC; 
  signal d_3_II_UIM : STD_LOGIC; 
  signal sp_d_3_MC_D1_PT_0 : STD_LOGIC; 
  signal sp_d_3_MC_D1 : STD_LOGIC; 
  signal sp_d_3_MC_D2 : STD_LOGIC; 
  signal sp_d_3_MC_BUFOE_OUT : STD_LOGIC; 
  signal sp_d_4_MC_Q : STD_LOGIC; 
  signal sp_d_4_MC_OE : STD_LOGIC; 
  signal sp_d_4_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal sp_d_4_MC_D : STD_LOGIC; 
  signal d_4_II_UIM : STD_LOGIC; 
  signal sp_d_4_MC_D1_PT_0 : STD_LOGIC; 
  signal sp_d_4_MC_D1 : STD_LOGIC; 
  signal sp_d_4_MC_D2 : STD_LOGIC; 
  signal sp_d_4_MC_BUFOE_OUT : STD_LOGIC; 
  signal sp_d_5_MC_Q : STD_LOGIC; 
  signal sp_d_5_MC_OE : STD_LOGIC; 
  signal sp_d_5_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal sp_d_5_MC_D : STD_LOGIC; 
  signal d_5_II_UIM : STD_LOGIC; 
  signal sp_d_5_MC_D1_PT_0 : STD_LOGIC; 
  signal sp_d_5_MC_D1 : STD_LOGIC; 
  signal sp_d_5_MC_D2 : STD_LOGIC; 
  signal sp_d_5_MC_BUFOE_OUT : STD_LOGIC; 
  signal sp_d_6_MC_Q : STD_LOGIC; 
  signal sp_d_6_MC_OE : STD_LOGIC; 
  signal sp_d_6_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal sp_d_6_MC_D : STD_LOGIC; 
  signal d_6_II_UIM : STD_LOGIC; 
  signal sp_d_6_MC_D1_PT_0 : STD_LOGIC; 
  signal sp_d_6_MC_D1 : STD_LOGIC; 
  signal sp_d_6_MC_D2 : STD_LOGIC; 
  signal sp_d_6_MC_BUFOE_OUT : STD_LOGIC; 
  signal sp_d_7_MC_Q : STD_LOGIC; 
  signal sp_d_7_MC_OE : STD_LOGIC; 
  signal sp_d_7_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal sp_d_7_MC_D : STD_LOGIC; 
  signal d_7_II_UIM : STD_LOGIC; 
  signal sp_d_7_MC_D1_PT_0 : STD_LOGIC; 
  signal sp_d_7_MC_D1 : STD_LOGIC; 
  signal sp_d_7_MC_D2 : STD_LOGIC; 
  signal sp_d_7_MC_BUFOE_OUT : STD_LOGIC; 
  signal sp_d_8_MC_Q : STD_LOGIC; 
  signal sp_d_8_MC_OE : STD_LOGIC; 
  signal sp_d_8_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal sp_d_8_MC_D : STD_LOGIC; 
  signal d_8_II_UIM : STD_LOGIC; 
  signal sp_d_8_MC_D1_PT_0 : STD_LOGIC; 
  signal sp_d_8_MC_D1 : STD_LOGIC; 
  signal sp_d_8_MC_D2 : STD_LOGIC; 
  signal sp_d_8_MC_BUFOE_OUT : STD_LOGIC; 
  signal sp_d_9_MC_Q : STD_LOGIC; 
  signal sp_d_9_MC_OE : STD_LOGIC; 
  signal sp_d_9_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal sp_d_9_MC_D : STD_LOGIC; 
  signal d_9_II_UIM : STD_LOGIC; 
  signal sp_d_9_MC_D1_PT_0 : STD_LOGIC; 
  signal sp_d_9_MC_D1 : STD_LOGIC; 
  signal sp_d_9_MC_D2 : STD_LOGIC; 
  signal sp_d_9_MC_BUFOE_OUT : STD_LOGIC; 
  signal sram_cs1n_MC_Q : STD_LOGIC; 
  signal sram_cs1n_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal sram_cs1n_MC_D : STD_LOGIC; 
  signal sram_cs1n_MC_D1 : STD_LOGIC; 
  signal sram_cs1n_MC_D2_PT_0 : STD_LOGIC; 
  signal sram_cs1n_MC_D2_PT_1 : STD_LOGIC; 
  signal sram_cs1n_MC_D2_PT_2 : STD_LOGIC; 
  signal sram_cs1n_MC_D2 : STD_LOGIC; 
  signal sram_low_byten_MC_Q : STD_LOGIC; 
  signal sram_low_byten_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal sram_low_byten_MC_D : STD_LOGIC; 
  signal sram_low_byten_MC_D1 : STD_LOGIC; 
  signal sram_low_byten_MC_D2 : STD_LOGIC; 
  signal sram_upper_byten_MC_Q : STD_LOGIC; 
  signal sram_upper_byten_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal sram_upper_byten_MC_D : STD_LOGIC; 
  signal sram_upper_byten_MC_D1 : STD_LOGIC; 
  signal sram_upper_byten_MC_D2 : STD_LOGIC; 
  signal GND : STD_LOGIC; 
  signal VCC : STD_LOGIC; 
  signal PRLD : STD_LOGIC; 
  signal NlwInverterSignal_a_0_MC_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_a_0_MC_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_FOOBAR6_ctinst_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_FOOBAR6_ctinst_0_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_FOOBAR6_ctinst_0_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_FOOBAR6_ctinst_4_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_FOOBAR6_ctinst_4_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_FOOBAR6_ctinst_4_IN2 : STD_LOGIC; 
  signal NlwInverterSig