top_level_timesim.vhd

8 Channel Digital Volt Meter

  signal busy_test_MC_D : STD_LOGIC; 
  signal busy_II_UIM : STD_LOGIC; 
  signal busy_test_MC_D1_PT_0 : STD_LOGIC; 
  signal busy_test_MC_D1 : STD_LOGIC; 
  signal busy_test_MC_D2 : STD_LOGIC; 
  signal chip3_en_MC_Q : STD_LOGIC; 
  signal chip3_en_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal chip3_en_MC_D : STD_LOGIC; 
  signal chip3_en_MC_D1_PT_0 : STD_LOGIC; 
  signal chip3_en_MC_D1 : STD_LOGIC; 
  signal chip3_en_MC_D2 : STD_LOGIC; 
  signal convert_MC_Q : STD_LOGIC; 
  signal convert_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal convert_MC_D : STD_LOGIC; 
  signal convert_MC_D1 : STD_LOGIC; 
  signal convert_MC_D2 : STD_LOGIC; 
  signal d_0_MC_Q : STD_LOGIC; 
  signal d_0_MC_OE : STD_LOGIC; 
  signal d_0_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal d_0_MC_D : STD_LOGIC; 
  signal d_0_MC_D1 : STD_LOGIC; 
  signal d_0_MC_D2_PT_0 : STD_LOGIC; 
  signal d_0_MC_D2_PT_1 : STD_LOGIC; 
  signal d_0_MC_D2 : STD_LOGIC; 
  signal d_0_MC_BUFOE_OUT : STD_LOGIC; 
  signal FOOBAR4_ctinst_0 : STD_LOGIC; 
  signal FOOBAR4_ctinst_1 : STD_LOGIC; 
  signal FOOBAR4_ctinst_4 : STD_LOGIC; 
  signal N813 : STD_LOGIC; 
  signal FOOBAR4_ctinst_7 : STD_LOGIC; 
  signal N813_MC_Q : STD_LOGIC; 
  signal N813_MC_D : STD_LOGIC; 
  signal N813_MC_D1 : STD_LOGIC; 
  signal sp_oen_II_UIM : STD_LOGIC; 
  signal N813_MC_D2_PT_0 : STD_LOGIC; 
  signal N813_MC_D2_PT_1 : STD_LOGIC; 
  signal N813_MC_D2 : STD_LOGIC; 
  signal d_10_MC_Q : STD_LOGIC; 
  signal d_10_MC_OE : STD_LOGIC; 
  signal d_10_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal d_10_MC_D : STD_LOGIC; 
  signal d_10_MC_D1 : STD_LOGIC; 
  signal N634 : STD_LOGIC; 
  signal d_10_MC_D2_PT_0 : STD_LOGIC; 
  signal d_10_MC_D2_PT_1 : STD_LOGIC; 
  signal d_10_MC_D2 : STD_LOGIC; 
  signal d_10_MC_BUFOE_OUT : STD_LOGIC; 
  signal N634_MC_Q : STD_LOGIC; 
  signal N634_MC_R_OR_PRLD : STD_LOGIC; 
  signal N634_MC_D : STD_LOGIC; 
  signal N774 : STD_LOGIC; 
  signal N634_MC_D1_PT_0 : STD_LOGIC; 
  signal N634_MC_D1 : STD_LOGIC; 
  signal N634_MC_D2 : STD_LOGIC; 
  signal N774_MC_Q : STD_LOGIC; 
  signal N774_MC_R_OR_PRLD : STD_LOGIC; 
  signal N774_MC_D : STD_LOGIC; 
  signal N764 : STD_LOGIC; 
  signal N774_MC_D1_PT_0 : STD_LOGIC; 
  signal N774_MC_D1 : STD_LOGIC; 
  signal N774_MC_D2 : STD_LOGIC; 
  signal N764_MC_Q : STD_LOGIC; 
  signal N764_MC_R_OR_PRLD : STD_LOGIC; 
  signal N764_MC_D : STD_LOGIC; 
  signal N754 : STD_LOGIC; 
  signal N764_MC_D1_PT_0 : STD_LOGIC; 
  signal N764_MC_D1 : STD_LOGIC; 
  signal N764_MC_D2 : STD_LOGIC; 
  signal N754_MC_Q : STD_LOGIC; 
  signal N754_MC_R_OR_PRLD : STD_LOGIC; 
  signal N754_MC_D : STD_LOGIC; 
  signal N744 : STD_LOGIC; 
  signal N754_MC_D1_PT_0 : STD_LOGIC; 
  signal N754_MC_D1 : STD_LOGIC; 
  signal N754_MC_D2 : STD_LOGIC; 
  signal N744_MC_Q : STD_LOGIC; 
  signal FOOBAR7_ctinst_0 : STD_LOGIC; 
  signal N744_MC_R_OR_PRLD : STD_LOGIC; 
  signal N744_MC_D : STD_LOGIC; 
  signal FOOBAR7_ctinst_4 : STD_LOGIC; 
  signal N734 : STD_LOGIC; 
  signal N744_MC_D1_PT_0 : STD_LOGIC; 
  signal N744_MC_D1 : STD_LOGIC; 
  signal N744_MC_D2 : STD_LOGIC; 
  signal N734_MC_Q : STD_LOGIC; 
  signal N734_MC_R_OR_PRLD : STD_LOGIC; 
  signal N734_MC_D : STD_LOGIC; 
  signal N724 : STD_LOGIC; 
  signal N734_MC_D1_PT_0 : STD_LOGIC; 
  signal N734_MC_D1 : STD_LOGIC; 
  signal N734_MC_D2 : STD_LOGIC; 
  signal N724_MC_Q : STD_LOGIC; 
  signal N724_MC_R_OR_PRLD : STD_LOGIC; 
  signal N724_MC_D : STD_LOGIC; 
  signal N714 : STD_LOGIC; 
  signal N724_MC_D1_PT_0 : STD_LOGIC; 
  signal N724_MC_D1 : STD_LOGIC; 
  signal N724_MC_D2 : STD_LOGIC; 
  signal N714_MC_Q : STD_LOGIC; 
  signal N714_MC_R_OR_PRLD : STD_LOGIC; 
  signal N714_MC_D : STD_LOGIC; 
  signal N704 : STD_LOGIC; 
  signal N714_MC_D1_PT_0 : STD_LOGIC; 
  signal N714_MC_D1 : STD_LOGIC; 
  signal N714_MC_D2 : STD_LOGIC; 
  signal N704_MC_Q : STD_LOGIC; 
  signal N704_MC_R_OR_PRLD : STD_LOGIC; 
  signal N704_MC_D : STD_LOGIC; 
  signal N694 : STD_LOGIC; 
  signal N704_MC_D1_PT_0 : STD_LOGIC; 
  signal N704_MC_D1 : STD_LOGIC; 
  signal N704_MC_D2 : STD_LOGIC; 
  signal N694_MC_Q : STD_LOGIC; 
  signal N694_MC_R_OR_PRLD : STD_LOGIC; 
  signal N694_MC_D : STD_LOGIC; 
  signal N694_MC_D1_PT_0 : STD_LOGIC; 
  signal N694_MC_D1 : STD_LOGIC; 
  signal N694_MC_D2 : STD_LOGIC; 
  signal d_11_MC_Q : STD_LOGIC; 
  signal d_11_MC_OE : STD_LOGIC; 
  signal d_11_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal d_11_MC_D : STD_LOGIC; 
  signal d_11_MC_D1 : STD_LOGIC; 
  signal N644 : STD_LOGIC; 
  signal d_11_MC_D2_PT_0 : STD_LOGIC; 
  signal d_11_MC_D2_PT_1 : STD_LOGIC; 
  signal d_11_MC_D2 : STD_LOGIC; 
  signal d_11_MC_BUFOE_OUT : STD_LOGIC; 
  signal N644_MC_Q : STD_LOGIC; 
  signal N644_MC_R_OR_PRLD : STD_LOGIC; 
  signal N644_MC_D : STD_LOGIC; 
  signal N644_MC_D1_PT_0 : STD_LOGIC; 
  signal N644_MC_D1 : STD_LOGIC; 
  signal N644_MC_D2 : STD_LOGIC; 
  signal d_12_MC_Q : STD_LOGIC; 
  signal d_12_MC_OE : STD_LOGIC; 
  signal d_12_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal d_12_MC_D : STD_LOGIC; 
  signal d_12_MC_D1 : STD_LOGIC; 
  signal N654 : STD_LOGIC; 
  signal d_12_MC_D2_PT_0 : STD_LOGIC; 
  signal d_12_MC_D2_PT_1 : STD_LOGIC; 
  signal d_12_MC_D2 : STD_LOGIC; 
  signal d_12_MC_BUFOE_OUT : STD_LOGIC; 
  signal N654_MC_Q : STD_LOGIC; 
  signal N654_MC_R_OR_PRLD : STD_LOGIC; 
  signal N654_MC_D : STD_LOGIC; 
  signal N654_MC_D1_PT_0 : STD_LOGIC; 
  signal N654_MC_D1 : STD_LOGIC; 
  signal N654_MC_D2 : STD_LOGIC; 
  signal d_13_MC_Q : STD_LOGIC; 
  signal d_13_MC_OE : STD_LOGIC; 
  signal d_13_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal d_13_MC_D : STD_LOGIC; 
  signal d_13_MC_D1 : STD_LOGIC; 
  signal N664 : STD_LOGIC; 
  signal d_13_MC_D2_PT_0 : STD_LOGIC; 
  signal d_13_MC_D2_PT_1 : STD_LOGIC; 
  signal d_13_MC_D2 : STD_LOGIC; 
  signal d_13_MC_BUFOE_OUT : STD_LOGIC; 
  signal N664_MC_Q : STD_LOGIC; 
  signal N664_MC_R_OR_PRLD : STD_LOGIC; 
  signal N664_MC_D : STD_LOGIC; 
  signal N664_MC_D1_PT_0 : STD_LOGIC; 
  signal N664_MC_D1 : STD_LOGIC; 
  signal N664_MC_D2 : STD_LOGIC; 
  signal d_14_MC_Q : STD_LOGIC; 
  signal d_14_MC_OE : STD_LOGIC; 
  signal d_14_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal d_14_MC_D : STD_LOGIC; 
  signal d_14_MC_D1 : STD_LOGIC; 
  signal N674 : STD_LOGIC; 
  signal d_14_MC_D2_PT_0 : STD_LOGIC; 
  signal d_14_MC_D2_PT_1 : STD_LOGIC; 
  signal d_14_MC_D2 : STD_LOGIC; 
  signal d_14_MC_BUFOE_OUT : STD_LOGIC; 
  signal N674_MC_Q : STD_LOGIC; 
  signal N674_MC_R_OR_PRLD : STD_LOGIC; 
  signal N674_MC_D : STD_LOGIC; 
  signal N674_MC_D1_PT_0 : STD_LOGIC; 
  signal N674_MC_D1 : STD_LOGIC; 
  signal N674_MC_D2 : STD_LOGIC; 
  signal d_15_MC_Q : STD_LOGIC; 
  signal d_15_MC_OE : STD_LOGIC; 
  signal d_15_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal d_15_MC_D : STD_LOGIC; 
  signal d_15_MC_D1 : STD_LOGIC; 
  signal N684 : STD_LOGIC; 
  signal d_15_MC_D2_PT_0 : STD_LOGIC; 
  signal d_15_MC_D2_PT_1 : STD_LOGIC; 
  signal d_15_MC_D2 : STD_LOGIC; 
  signal d_15_MC_BUFOE_OUT : STD_LOGIC; 
  signal N684_MC_Q : STD_LOGIC; 
  signal N684_MC_R_OR_PRLD : STD_LOGIC; 
  signal N684_MC_D : STD_LOGIC; 
  signal N684_MC_D1_PT_0 : STD_LOGIC; 
  signal N684_MC_D1 : STD_LOGIC; 
  signal N684_MC_D2 : STD_LOGIC; 
  signal d_1_MC_Q : STD_LOGIC; 
  signal d_1_MC_OE : STD_LOGIC; 
  signal d_1_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal d_1_MC_D : STD_LOGIC; 
  signal d_1_MC_D1 : STD_LOGIC; 
  signal d_1_MC_D2_PT_0 : STD_LOGIC; 
  signal d_1_MC_D2_PT_1 : STD_LOGIC; 
  signal d_1_MC_D2 : STD_LOGIC; 
  signal d_1_MC_BUFOE_OUT : STD_LOGIC; 
  signal d_2_MC_Q : STD_LOGIC; 
  signal d_2_MC_OE : STD_LOGIC; 
  signal d_2_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal d_2_MC_D : STD_LOGIC; 
  signal d_2_MC_D1 : STD_LOGIC; 
  signal d_2_MC_D2_PT_0 : STD_LOGIC; 
  signal d_2_MC_D2_PT_1 : STD_LOGIC; 
  signal d_2_MC_D2 : STD_LOGIC; 
  signal d_2_MC_BUFOE_OUT : STD_LOGIC; 
  signal d_3_MC_Q : STD_LOGIC; 
  signal d_3_MC_OE : STD_LOGIC; 
  signal d_3_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal d_3_MC_D : STD_LOGIC; 
  signal d_3_MC_D1 : STD_LOGIC; 
  signal d_3_MC_D2_PT_0 : STD_LOGIC; 
  signal d_3_MC_D2_PT_1 : STD_LOGIC; 
  signal d_3_MC_D2 : STD_LOGIC; 
  signal d_3_MC_BUFOE_OUT : STD_LOGIC; 
  signal d_4_MC_Q : STD_LOGIC; 
  signal d_4_MC_OE : STD_LOGIC; 
  signal d_4_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal d_4_MC_D : STD_LOGIC; 
  signal d_4_MC_D1 : STD_LOGIC; 
  signal d_4_MC_D2_PT_0 : STD_LOGIC; 
  signal d_4_MC_D2_PT_1 : STD_LOGIC; 
  signal d_4_MC_D2 : STD_LOGIC; 
  signal d_4_MC_BUFOE_OUT : STD_LOGIC; 
  signal d_5_MC_Q : STD_LOGIC; 
  signal d_5_MC_OE : STD_LOGIC; 
  signal d_5_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal d_5_MC_D : STD_LOGIC; 
  signal d_5_MC_D1 : STD_LOGIC; 
  signal d_5_MC_D2_PT_0 : STD_LOGIC; 
  signal d_5_MC_D2_PT_1 : STD_LOGIC; 
  signal d_5_MC_D2 : STD_LOGIC; 
  signal d_5_MC_BUFOE_OUT : STD_LOGIC; 
  signal d_6_MC_Q : STD_LOGIC; 
  signal d_6_MC_OE : STD_LOGIC; 
  signal d_6_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal d_6_MC_D : STD_LOGIC; 
  signal d_6_MC_D1 : STD_LOGIC; 
  signal d_6_MC_D2_PT_0 : STD_LOGIC; 
  signal d_6_MC_D2_PT_1 : STD_LOGIC; 
  signal d_6_MC_D2 : STD_LOGIC; 
  signal d_6_MC_BUFOE_OUT : STD_LOGIC; 
  signal d_7_MC_Q : STD_LOGIC; 
  signal d_7_MC_OE : STD_LOGIC; 
  signal d_7_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal d_7_MC_D : STD_LOGIC; 
  signal d_7_MC_D1 : STD_LOGIC; 
  signal d_7_MC_D2_PT_0 : STD_LOGIC; 
  signal d_7_MC_D2_PT_1 : STD_LOGIC; 
  signal d_7_MC_D2 : STD_LOGIC; 
  signal d_7_MC_BUFOE_OUT : STD_LOGIC; 
  signal d_8_MC_Q : STD_LOGIC; 
  signal d_8_MC_OE : STD_LOGIC; 
  signal d_8_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal d_8_MC_D : STD_LOGIC; 
  signal d_8_MC_D1 : STD_LOGIC; 
  signal d_8_MC_D2_PT_0 : STD_LOGIC; 
  signal d_8_MC_D2_PT_1 : STD_LOGIC; 
  signal d_8_MC_D2 : STD_LOGIC; 
  signal d_8_MC_BUFOE_OUT : STD_LOGIC; 
  signal d_9_MC_Q : STD_LOGIC; 
  signal d_9_MC_OE : STD_LOGIC; 
  signal d_9_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal d_9_MC_D : STD_LOGIC; 
  signal d_9_MC_D1 : STD_LOGIC; 
  signal d_9_MC_D2_PT_0 : STD_LOGIC; 
  signal d_9_MC_D2_PT_1 : STD_LOGIC; 
  signal d_9_MC_D2 : STD_LOGIC; 
  signal d_9_MC_BUFOE_OUT : STD_LOGIC; 
  signal din_MC_Q : STD_LOGIC; 
  signal din_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal din_MC_D : STD_LOGIC; 
  signal din_MC_CE : STD_LOGIC; 
  signal din_MC_CE_PT_0 : STD_LOGIC; 
  signal dvm_N5442 : STD_LOGIC; 
  signal din_MC_D1_PT_0 : STD_LOGIC; 
  signal din_MC_D1 : STD_LOGIC; 
  signal din_MC_D2 : STD_LOGIC; 
  signal dvm_N5442_MC_Q : STD_LOGIC; 
  signal dvm_N5442_MC_D : STD_LOGIC; 
  signal dvm_N5442_MC_D1 : STD_LOGIC; 
  signal dvm_shift_data_N133 : STD_LOGIC; 
  signal dvm_N5442_MC_D2_PT_0 : STD_LOGIC; 
  signal dvm_N5443 : STD_LOGIC; 
  signal dvm_N5442_MC_D2_PT_1 : STD_LOGIC; 
  signal dvm_N5442_MC_D2_PT_2 : STD_LOGIC; 
  signal dvm_wr_reg_num_2 : STD_LOGIC; 
  signal dvm_N5442_MC_D2_PT_3 : STD_LOGIC; 
  signal dvm_wr_reg_num_0 : STD_LOGIC; 
  signal dvm_wr_reg_num_1 : STD_LOGIC; 
  signal dvm_N5442_MC_D2_PT_4 : STD_LOGIC; 
  signal dvm_N5442_MC_D2_PT_5 : STD_LOGIC; 
  signal dvm_N5442_MC_D2_PT_6 : STD_LOGIC; 
  signal dvm_N5442_MC_D2 : STD_LOGIC; 
  signal dvm_shift_data_N133_MC_Q : STD_LOGIC; 
  signal dvm_shift_data_N133_MC_D : STD_LOGIC; 
  signal dvm_shift_data_N133_MC_D1 : STD_LOGIC; 
  signal dvm_shift_data_N133_MC_D2_PT_0 : STD_LOGIC; 
  signal dvm_shift_data_N133_MC_D2_PT_1 : STD_LOGIC; 
  signal dvm_shift_data_N133_MC_D2 : STD_LOGIC; 
  signal dvm_N5443_MC_Q : STD_LOGIC; 
  signal dvm_N5443_MC_D : STD_LOGIC; 
  signal dvm_N5443_MC_D1 : STD_LOGIC; 
  signal dvm_N5443_MC_D2_PT_0 : STD_LOGIC; 
  signal dvm_N5444 : STD_LOGIC; 
  signal dvm_N5443_MC_D2_PT_1 : STD_LOGIC; 
  signal dvm_N5443_MC_D2_PT_2 : STD_LOGIC; 
  signal dvm_N5443_MC_D2_PT_3 : STD_LOGIC; 
  signal dvm_N5443_MC_D2 : STD_LOGIC; 
  signal dvm_N5444_MC_Q : STD_LOGIC; 
  signal dvm_N5444_MC_D : STD_LOGIC; 
  signal dvm_N5444_MC_D1 : STD_LOGIC; 
  signal dvm_N5444_MC_D2_PT_0 : STD_LOGIC; 
  signal dvm_N5445 : STD_LOGIC; 
  signal dvm_N5444_MC_D2_PT_1 : STD_LOGIC; 
  signal dvm_N5444_MC_D2_PT_2 : STD_LOGIC; 
  signal dvm_N5444_MC_D2_PT_3 : STD_LOGIC; 
  signal dvm_N5444_MC_D2_PT_4 : STD_LOGIC; 
  signal dvm_N5444_MC_D2 : STD_LOGIC; 
  signal dvm_N5445_MC_Q : STD_LOGIC; 
  signal dvm_N5445_MC_D : STD_LOGIC; 
  signal dvm_N5445_MC_D1 : STD_LOGIC; 
  signal dvm_N5445_MC_D2_PT_0 : STD_LOGIC; 
  signal dvm_N5446 : STD_LOGIC; 
  signal dvm_N5445_MC_D2_PT_1 : STD_LOGIC; 
  signal dvm_N5445_MC_D2_PT_2 : STD_LOGIC;