top_level_timesim.vhd

8 Channel Digital Volt Meter

  signal N463_MC_R_OR_PRLD : STD_LOGIC; 
  signal N463_MC_D : STD_LOGIC; 
  signal N463_MC_D1 : STD_LOGIC; 
  signal N_PZ_597 : STD_LOGIC; 
  signal N463_MC_D2_PT_0 : STD_LOGIC; 
  signal N463_MC_D2_PT_1 : STD_LOGIC; 
  signal N463_MC_D2 : STD_LOGIC; 
  signal N463_MC_D_TFF : STD_LOGIC; 
  signal N_PZ_597_MC_Q : STD_LOGIC; 
  signal N_PZ_597_MC_D : STD_LOGIC; 
  signal N_PZ_597_MC_D1 : STD_LOGIC; 
  signal N_PZ_597_MC_D2_PT_0 : STD_LOGIC; 
  signal N_PZ_597_MC_D2_PT_1 : STD_LOGIC; 
  signal N_PZ_597_MC_D2_PT_2 : STD_LOGIC; 
  signal N_PZ_597_MC_D2_PT_3 : STD_LOGIC; 
  signal N_PZ_597_MC_D2 : STD_LOGIC; 
  signal N483_MC_Q : STD_LOGIC; 
  signal N483_MC_R_OR_PRLD : STD_LOGIC; 
  signal N483_MC_D : STD_LOGIC; 
  signal N483_MC_D1 : STD_LOGIC; 
  signal N483_MC_D2_PT_0 : STD_LOGIC; 
  signal N483_MC_D2_PT_1 : STD_LOGIC; 
  signal N483_MC_D2 : STD_LOGIC; 
  signal N483_MC_D_TFF : STD_LOGIC; 
  signal N493_MC_Q : STD_LOGIC; 
  signal N493_MC_R_OR_PRLD : STD_LOGIC; 
  signal N493_MC_D : STD_LOGIC; 
  signal N493_MC_D1 : STD_LOGIC; 
  signal N493_MC_D2_PT_0 : STD_LOGIC; 
  signal N493_MC_D2_PT_1 : STD_LOGIC; 
  signal N493_MC_D2_PT_2 : STD_LOGIC; 
  signal N493_MC_D2 : STD_LOGIC; 
  signal N503_MC_Q : STD_LOGIC; 
  signal N503_MC_R_OR_PRLD : STD_LOGIC; 
  signal N503_MC_D : STD_LOGIC; 
  signal N503_MC_D1 : STD_LOGIC; 
  signal N503_MC_D2_PT_0 : STD_LOGIC; 
  signal N503_MC_D2_PT_1 : STD_LOGIC; 
  signal N503_MC_D2_PT_2 : STD_LOGIC; 
  signal N503_MC_D2_PT_3 : STD_LOGIC; 
  signal N503_MC_D2 : STD_LOGIC; 
  signal dvm_dm_sng_ln7_flag_MC_Q : STD_LOGIC; 
  signal dvm_dm_sng_ln7_flag_MC_D : STD_LOGIC; 
  signal dvm_dm_sng_ln7_flag_MC_D1 : STD_LOGIC; 
  signal dvm_dm_sng_ln7_flag_MC_D2_PT_0 : STD_LOGIC; 
  signal dvm_dm_sng_ln7_flag_MC_D2_PT_1 : STD_LOGIC; 
  signal dvm_dm_sng_ln7_flag_MC_D2 : STD_LOGIC; 
  signal FOOBAR2_ctinst_7 : STD_LOGIC; 
  signal dvm_N1821_MC_Q : STD_LOGIC; 
  signal dvm_N1821_MC_D : STD_LOGIC; 
  signal dvm_N1821_MC_D1_PT_0 : STD_LOGIC; 
  signal dvm_N1821_MC_D1 : STD_LOGIC; 
  signal dvm_N1821_MC_D2 : STD_LOGIC; 
  signal dvm_N1955_MC_Q : STD_LOGIC; 
  signal dvm_N1955_MC_D : STD_LOGIC; 
  signal dvm_N1955_MC_D1_PT_0 : STD_LOGIC; 
  signal dvm_N1955_MC_D1 : STD_LOGIC; 
  signal dvm_N1955_MC_D2 : STD_LOGIC; 
  signal dvm_N1868_MC_Q : STD_LOGIC; 
  signal dvm_N1868_MC_D : STD_LOGIC; 
  signal dvm_N1868_MC_D1_PT_0 : STD_LOGIC; 
  signal dvm_N1868_MC_D1 : STD_LOGIC; 
  signal dvm_N1868_MC_D2 : STD_LOGIC; 
  signal dvm_N2005_MC_Q : STD_LOGIC; 
  signal dvm_N2005_MC_D : STD_LOGIC; 
  signal dvm_N2005_MC_D1_PT_0 : STD_LOGIC; 
  signal dvm_N2005_MC_D1 : STD_LOGIC; 
  signal dvm_N2005_MC_D2 : STD_LOGIC; 
  signal N_PZ_570_MC_Q : STD_LOGIC; 
  signal N_PZ_570_MC_D : STD_LOGIC; 
  signal N_PZ_570_MC_D1_PT_0 : STD_LOGIC; 
  signal N_PZ_570_MC_D1 : STD_LOGIC; 
  signal N_PZ_570_MC_D2 : STD_LOGIC; 
  signal dvm_N1007_MC_D1_PT_0 : STD_LOGIC; 
  signal dvm_N1007_MC_D1 : STD_LOGIC; 
  signal dvm_N1007_MC_D2 : STD_LOGIC; 
  signal dvm_wr_addr3_flag_MC_Q : STD_LOGIC; 
  signal dvm_wr_addr3_flag_MC_D : STD_LOGIC; 
  signal dvm_wr_addr3_flag_MC_D1 : STD_LOGIC; 
  signal dvm_wr_addr3_flag_MC_D2_PT_0 : STD_LOGIC; 
  signal dvm_wr_addr3_flag_MC_D2_PT_1 : STD_LOGIC; 
  signal dvm_wr_addr3_flag_MC_D2 : STD_LOGIC; 
  signal dvm_wr_addr4_flag_MC_Q : STD_LOGIC; 
  signal dvm_wr_addr4_flag_MC_R_OR_PRLD : STD_LOGIC; 
  signal dvm_wr_addr4_flag_MC_D : STD_LOGIC; 
  signal dvm_wr_addr4_flag_MC_D1 : STD_LOGIC; 
  signal dvm_wr_addr4_flag_MC_D2_PT_0 : STD_LOGIC; 
  signal dvm_wr_addr4_flag_MC_D2_PT_1 : STD_LOGIC; 
  signal dvm_wr_addr4_flag_MC_D2 : STD_LOGIC; 
  signal dvm_wr_addr4_flag_MC_D_TFF : STD_LOGIC; 
  signal dvm_wr_addr7_flag_MC_Q : STD_LOGIC; 
  signal dvm_wr_addr7_flag_MC_D : STD_LOGIC; 
  signal dvm_wr_addr7_flag_MC_D1 : STD_LOGIC; 
  signal dvm_wr_addr7_flag_MC_D2_PT_0 : STD_LOGIC; 
  signal dvm_wr_addr7_flag_MC_D2_PT_1 : STD_LOGIC; 
  signal dvm_wr_addr7_flag_MC_D2 : STD_LOGIC; 
  signal dvm_wr_addr5_flag_MC_Q : STD_LOGIC; 
  signal dvm_wr_addr5_flag_MC_D : STD_LOGIC; 
  signal dvm_wr_addr5_flag_MC_D1 : STD_LOGIC; 
  signal dvm_wr_addr5_flag_MC_D2_PT_0 : STD_LOGIC; 
  signal dvm_wr_addr5_flag_MC_D2_PT_1 : STD_LOGIC; 
  signal dvm_wr_addr5_flag_MC_D2 : STD_LOGIC; 
  signal dvm_wr_addr6_flag_MC_Q : STD_LOGIC; 
  signal dvm_wr_addr6_flag_MC_D : STD_LOGIC; 
  signal dvm_wr_addr6_flag_MC_D1 : STD_LOGIC; 
  signal dvm_wr_addr6_flag_MC_D2_PT_0 : STD_LOGIC; 
  signal dvm_wr_addr6_flag_MC_D2_PT_1 : STD_LOGIC; 
  signal dvm_wr_addr6_flag_MC_D2 : STD_LOGIC; 
  signal dvm_wr_addr24_flag_MC_Q : STD_LOGIC; 
  signal dvm_wr_addr24_flag_MC_R_OR_PRLD : STD_LOGIC; 
  signal dvm_wr_addr24_flag_MC_D : STD_LOGIC; 
  signal dvm_wr_addr24_flag_MC_D1 : STD_LOGIC; 
  signal dvm_wr_addr24_flag_MC_D2_PT_0 : STD_LOGIC; 
  signal dvm_wr_addr24_flag_MC_D2_PT_1 : STD_LOGIC; 
  signal dvm_wr_addr24_flag_MC_D2_PT_2 : STD_LOGIC; 
  signal dvm_wr_addr24_flag_MC_D2 : STD_LOGIC; 
  signal reset_button_MC_Q : STD_LOGIC; 
  signal reset_button_MC_D : STD_LOGIC; 
  signal FOOBAR14_ctinst_4 : STD_LOGIC; 
  signal sp_a_10_II_UIM : STD_LOGIC; 
  signal sp_a_11_II_UIM : STD_LOGIC; 
  signal sp_a_12_II_UIM : STD_LOGIC; 
  signal sp_a_13_II_UIM : STD_LOGIC; 
  signal sp_a_14_II_UIM : STD_LOGIC; 
  signal sp_a_7_II_UIM : STD_LOGIC; 
  signal sp_a_8_II_UIM : STD_LOGIC; 
  signal sp_a_9_II_UIM : STD_LOGIC; 
  signal sp_a_15_II_UIM : STD_LOGIC; 
  signal sp_a_16_II_UIM : STD_LOGIC; 
  signal sp_a_17_II_UIM : STD_LOGIC; 
  signal sp_a_18_II_UIM : STD_LOGIC; 
  signal sp_a_19_II_UIM : STD_LOGIC; 
  signal sp_a_20_II_UIM : STD_LOGIC; 
  signal sp_a_21_II_UIM : STD_LOGIC; 
  signal sp_a_22_II_UIM : STD_LOGIC; 
  signal sp_a_2_II_UIM : STD_LOGIC; 
  signal sp_a_3_II_UIM : STD_LOGIC; 
  signal sp_a_4_II_UIM : STD_LOGIC; 
  signal sp_a_5_II_UIM : STD_LOGIC; 
  signal sp_a_23_II_UIM : STD_LOGIC; 
  signal sp_a_6_II_UIM : STD_LOGIC; 
  signal N_PZ_550 : STD_LOGIC; 
  signal reset_button_MC_D1_PT_0 : STD_LOGIC; 
  signal reset_button_MC_D1 : STD_LOGIC; 
  signal reset_button_MC_D2 : STD_LOGIC; 
  signal reset_button_MC_D_TFF : STD_LOGIC; 
  signal N_PZ_550_MC_Q : STD_LOGIC; 
  signal N_PZ_550_MC_D : STD_LOGIC; 
  signal N_PZ_550_MC_D1 : STD_LOGIC; 
  signal sp_d_10_II_UIM : STD_LOGIC; 
  signal sp_d_11_II_UIM : STD_LOGIC; 
  signal sp_d_12_II_UIM : STD_LOGIC; 
  signal sp_d_13_II_UIM : STD_LOGIC; 
  signal sp_d_14_II_UIM : STD_LOGIC; 
  signal sp_d_15_II_UIM : STD_LOGIC; 
  signal sp_d_8_II_UIM : STD_LOGIC; 
  signal sp_d_9_II_UIM : STD_LOGIC; 
  signal sp_d_0_II_UIM : STD_LOGIC; 
  signal sp_d_1_II_UIM : STD_LOGIC; 
  signal sp_d_2_II_UIM : STD_LOGIC; 
  signal sp_d_3_II_UIM : STD_LOGIC; 
  signal sp_d_4_II_UIM : STD_LOGIC; 
  signal sp_d_5_II_UIM : STD_LOGIC; 
  signal sp_d_6_II_UIM : STD_LOGIC; 
  signal sp_d_7_II_UIM : STD_LOGIC; 
  signal N_PZ_550_MC_D2_PT_0 : STD_LOGIC; 
  signal N_PZ_550_MC_D2_PT_1 : STD_LOGIC; 
  signal N_PZ_550_MC_D2 : STD_LOGIC; 
  signal N363_MC_D1_PT_0 : STD_LOGIC; 
  signal N363_MC_D1 : STD_LOGIC; 
  signal N363_MC_D2_PT_0 : STD_LOGIC; 
  signal N363_MC_D2_PT_1 : STD_LOGIC; 
  signal N363_MC_D2 : STD_LOGIC; 
  signal N363_MC_D_TFF : STD_LOGIC; 
  signal a_10_MC_Q : STD_LOGIC; 
  signal a_10_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal a_10_MC_D : STD_LOGIC; 
  signal a_10_MC_D1 : STD_LOGIC; 
  signal a_10_MC_D2_PT_0 : STD_LOGIC; 
  signal a_10_MC_D2_PT_1 : STD_LOGIC; 
  signal a_10_MC_D2 : STD_LOGIC; 
  signal a_11_MC_Q : STD_LOGIC; 
  signal a_11_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal a_11_MC_D : STD_LOGIC; 
  signal a_11_MC_D1 : STD_LOGIC; 
  signal a_11_MC_D2_PT_0 : STD_LOGIC; 
  signal a_11_MC_D2_PT_1 : STD_LOGIC; 
  signal a_11_MC_D2 : STD_LOGIC; 
  signal a_12_MC_Q : STD_LOGIC; 
  signal a_12_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal a_12_MC_D : STD_LOGIC; 
  signal a_12_MC_D1 : STD_LOGIC; 
  signal a_12_MC_D2_PT_0 : STD_LOGIC; 
  signal a_12_MC_D2_PT_1 : STD_LOGIC; 
  signal a_12_MC_D2 : STD_LOGIC; 
  signal a_13_MC_Q : STD_LOGIC; 
  signal a_13_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal a_13_MC_D : STD_LOGIC; 
  signal a_13_MC_D1 : STD_LOGIC; 
  signal a_13_MC_D2_PT_0 : STD_LOGIC; 
  signal a_13_MC_D2_PT_1 : STD_LOGIC; 
  signal a_13_MC_D2 : STD_LOGIC; 
  signal a_14_MC_Q : STD_LOGIC; 
  signal a_14_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal a_14_MC_D : STD_LOGIC; 
  signal a_14_MC_D1 : STD_LOGIC; 
  signal a_14_MC_D2_PT_0 : STD_LOGIC; 
  signal a_14_MC_D2_PT_1 : STD_LOGIC; 
  signal a_14_MC_D2 : STD_LOGIC; 
  signal a_15_MC_Q : STD_LOGIC; 
  signal a_15_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal a_15_MC_D : STD_LOGIC; 
  signal a_15_MC_D1 : STD_LOGIC; 
  signal a_15_MC_D2_PT_0 : STD_LOGIC; 
  signal a_15_MC_D2_PT_1 : STD_LOGIC; 
  signal a_15_MC_D2 : STD_LOGIC; 
  signal a_16_MC_Q : STD_LOGIC; 
  signal a_16_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal a_16_MC_D : STD_LOGIC; 
  signal a_16_MC_D1 : STD_LOGIC; 
  signal a_16_MC_D2_PT_0 : STD_LOGIC; 
  signal a_16_MC_D2_PT_1 : STD_LOGIC; 
  signal a_16_MC_D2 : STD_LOGIC; 
  signal a_17_MC_Q : STD_LOGIC; 
  signal a_17_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal a_17_MC_D : STD_LOGIC; 
  signal a_17_MC_D1 : STD_LOGIC; 
  signal a_17_MC_D2_PT_0 : STD_LOGIC; 
  signal a_17_MC_D2_PT_1 : STD_LOGIC; 
  signal a_17_MC_D2 : STD_LOGIC; 
  signal a_18_MC_Q : STD_LOGIC; 
  signal a_18_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal a_18_MC_D : STD_LOGIC; 
  signal a_18_MC_D1 : STD_LOGIC; 
  signal a_18_MC_D2_PT_0 : STD_LOGIC; 
  signal a_18_MC_D2_PT_1 : STD_LOGIC; 
  signal a_18_MC_D2 : STD_LOGIC; 
  signal a_19_MC_Q : STD_LOGIC; 
  signal a_19_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal a_19_MC_D : STD_LOGIC; 
  signal a_19_MC_D1 : STD_LOGIC; 
  signal a_19_MC_D2_PT_0 : STD_LOGIC; 
  signal a_19_MC_D2_PT_1 : STD_LOGIC; 
  signal a_19_MC_D2 : STD_LOGIC; 
  signal a_1_MC_Q : STD_LOGIC; 
  signal a_1_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal a_1_MC_D : STD_LOGIC; 
  signal a_1_MC_D1 : STD_LOGIC; 
  signal a_1_MC_D2_PT_0 : STD_LOGIC; 
  signal a_1_MC_D2_PT_1 : STD_LOGIC; 
  signal a_1_MC_D2 : STD_LOGIC; 
  signal a_20_MC_Q : STD_LOGIC; 
  signal a_20_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal a_20_MC_D : STD_LOGIC; 
  signal a_20_MC_D1 : STD_LOGIC; 
  signal a_20_MC_D2_PT_0 : STD_LOGIC; 
  signal a_20_MC_D2_PT_1 : STD_LOGIC; 
  signal a_20_MC_D2 : STD_LOGIC; 
  signal a_21_MC_Q : STD_LOGIC; 
  signal a_21_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal a_21_MC_D : STD_LOGIC; 
  signal a_21_MC_D1 : STD_LOGIC; 
  signal a_21_MC_D2_PT_0 : STD_LOGIC; 
  signal a_21_MC_D2_PT_1 : STD_LOGIC; 
  signal a_21_MC_D2 : STD_LOGIC; 
  signal a_22_MC_Q : STD_LOGIC; 
  signal a_22_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal a_22_MC_D : STD_LOGIC; 
  signal a_22_MC_D1 : STD_LOGIC; 
  signal a_22_MC_D2_PT_0 : STD_LOGIC; 
  signal a_22_MC_D2_PT_1 : STD_LOGIC; 
  signal a_22_MC_D2 : STD_LOGIC; 
  signal a_2_MC_Q : STD_LOGIC; 
  signal a_2_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal a_2_MC_D : STD_LOGIC; 
  signal a_2_MC_D1 : STD_LOGIC; 
  signal a_2_MC_D2_PT_0 : STD_LOGIC; 
  signal a_2_MC_D2_PT_1 : STD_LOGIC; 
  signal a_2_MC_D2 : STD_LOGIC; 
  signal a_3_MC_Q : STD_LOGIC; 
  signal a_3_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal a_3_MC_D : STD_LOGIC; 
  signal a_3_MC_D1 : STD_LOGIC; 
  signal a_3_MC_D2_PT_0 : STD_LOGIC; 
  signal a_3_MC_D2_PT_1 : STD_LOGIC; 
  signal a_3_MC_D2 : STD_LOGIC; 
  signal a_4_MC_Q : STD_LOGIC; 
  signal a_4_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal a_4_MC_D : STD_LOGIC; 
  signal a_4_MC_D1 : STD_LOGIC; 
  signal a_4_MC_D2_PT_0 : STD_LOGIC; 
  signal a_4_MC_D2_PT_1 : STD_LOGIC; 
  signal a_4_MC_D2 : STD_LOGIC; 
  signal a_5_MC_Q : STD_LOGIC; 
  signal a_5_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal a_5_MC_D : STD_LOGIC; 
  signal a_5_MC_D1 : STD_LOGIC; 
  signal a_5_MC_D2_PT_0 : STD_LOGIC; 
  signal a_5_MC_D2_PT_1 : STD_LOGIC; 
  signal a_5_MC_D2 : STD_LOGIC; 
  signal a_6_MC_Q : STD_LOGIC; 
  signal a_6_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal a_6_MC_D : STD_LOGIC; 
  signal a_6_MC_D1 : STD_LOGIC; 
  signal a_6_MC_D2_PT_0 : STD_LOGIC; 
  signal a_6_MC_D2_PT_1 : STD_LOGIC; 
  signal a_6_MC_D2 : STD_LOGIC; 
  signal a_7_MC_Q : STD_LOGIC; 
  signal a_7_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal a_7_MC_D : STD_LOGIC; 
  signal a_7_MC_D1 : STD_LOGIC; 
  signal a_7_MC_D2_PT_0 : STD_LOGIC; 
  signal a_7_MC_D2_PT_1 : STD_LOGIC; 
  signal a_7_MC_D2 : STD_LOGIC; 
  signal a_8_MC_Q : STD_LOGIC; 
  signal a_8_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal a_8_MC_D : STD_LOGIC; 
  signal a_8_MC_D1 : STD_LOGIC; 
  signal a_8_MC_D2_PT_0 : STD_LOGIC; 
  signal a_8_MC_D2_PT_1 : STD_LOGIC; 
  signal a_8_MC_D2 : STD_LOGIC; 
  signal a_9_MC_Q : STD_LOGIC; 
  signal a_9_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal a_9_MC_D : STD_LOGIC; 
  signal a_9_MC_D1 : STD_LOGIC; 
  signal a_9_MC_D2_PT_0 : STD_LOGIC; 
  signal a_9_MC_D2_PT_1 : STD_LOGIC; 
  signal a_9_MC_D2 : STD_LOGIC; 
  signal ad_chip2_enn_MC_Q : STD_LOGIC; 
  signal ad_chip2_enn_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal ad_chip2_enn_MC_D : STD_LOGIC; 
  signal ad_chip2_enn_MC_D1_PT_0 : STD_LOGIC; 
  signal ad_chip2_enn_MC_D1 : STD_LOGIC; 
  signal ad_chip2_enn_MC_D2 : STD_LOGIC; 
  signal busy_test_MC_Q : STD_LOGIC; 
  signal busy_test_MC_Q_tsim_ireg_Q : STD_LOGIC;