top_level_timesim.vhd

8 Channel Digital Volt Meter

-- Xilinx Vhdl produced by program ngd2vhdl E.33
-- Command: -rpw 100 -tpw 1 -ar Structure -xon true -w top_level.nga top_level_timesim.vhd 
-- Input file: top_level.nga
-- Output file: top_level_timesim.vhd
-- Design name: top_level
-- Xilinx: C:/xilinx_webpack
-- # of Entities: 1
-- Device: XCR3256XL-7-CS280

-- The output of ngd2vhdl is a simulation model. This file cannot be synthesized,
-- or used in any other manner other than simulation. This netlist uses simulation
-- primitives which may not represent the true implementation of the device, however
-- the netlist is functionally correct. Do not modify this file.

-- Model for  ROC (Reset-On-Configuration) Cell
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
entity ROC is
  generic (InstancePath: STRING := "*";
           WIDTH : Time := 100 ns);
  port(O : out std_ulogic := '1') ;
  attribute VITAL_LEVEL0 of ROC : entity is TRUE;
end ROC;

architecture ROC_V of ROC is
attribute VITAL_LEVEL0 of ROC_V : architecture is TRUE;
begin
  ONE_SHOT : process
  begin
    if (WIDTH <= 0 ns) then
       assert FALSE report
       "*** Error: a positive value of WIDTH must be specified ***"
       severity failure;
    else
       wait for WIDTH;
       O <= '0';
    end if;
    wait;
  end process ONE_SHOT;
end ROC_V;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library SIMPRIM;
use SIMPRIM.VCOMPONENTS.ALL;
use SIMPRIM.VPACKAGE.ALL;
entity top_level is
  port (
    cclk : in STD_LOGIC := 'X'; 
    sp_cs1n : in STD_LOGIC := 'X'; 
    sp_wen : in STD_LOGIC := 'X'; 
    ad_chip2_enn : out STD_LOGIC; 
    busy : in STD_LOGIC := 'X'; 
    busy_test : out STD_LOGIC; 
    chip3_en : out STD_LOGIC; 
    convert : out STD_LOGIC; 
    sp_cs0n : in STD_LOGIC := 'X'; 
    din : out STD_LOGIC; 
    flash_cs0n : out STD_LOGIC; 
    flash_wr_protect : out STD_LOGIC; 
    io13 : out STD_LOGIC; 
    led1_sel : out STD_LOGIC; 
    led2_sel : out STD_LOGIC; 
    led3_sel : out STD_LOGIC; 
    led4_sel : out STD_LOGIC; 
    sp_oen : in STD_LOGIC := 'X'; 
    oen : out STD_LOGIC; 
    osc_cntrl : out STD_LOGIC; 
    reset_adn : out STD_LOGIC; 
    reset_memn : out STD_LOGIC; 
    rise_fall : out STD_LOGIC; 
    rwn : out STD_LOGIC; 
    sclk : out STD_LOGIC; 
    sp_a_0 : out STD_LOGIC; 
    sram_cs1n : out STD_LOGIC; 
    sram_low_byten : out STD_LOGIC; 
    sram_upper_byten : out STD_LOGIC; 
    dout : in STD_LOGIC := 'X'; 
    sp_a : in STD_LOGIC_VECTOR ( 23 downto 1 ); 
    sp_d : inout STD_LOGIC_VECTOR ( 15 downto 0 ); 
    a : out STD_LOGIC_VECTOR ( 22 downto 0 ); 
    d : inout STD_LOGIC_VECTOR ( 15 downto 0 ) 
  );
end top_level;

architecture Structure of top_level is
  component ROC
    generic (InstancePath: STRING := "*";
             WIDTH : Time := 100 ns);
    port (O : out STD_ULOGIC := '1');
  end component;
  signal a_0_MC_Q : STD_LOGIC; 
  signal a_0_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal a_0_MC_D : STD_LOGIC; 
  signal a_0_MC_D1 : STD_LOGIC; 
  signal N363 : STD_LOGIC; 
  signal N_PZ_450 : STD_LOGIC; 
  signal a_0_MC_D2_PT_0 : STD_LOGIC; 
  signal sp_a_1_II_UIM : STD_LOGIC; 
  signal dvm_main_curr_state_FFD4 : STD_LOGIC; 
  signal dvm_main_curr_state_FFD1 : STD_LOGIC; 
  signal dvm_main_curr_state_FFD3 : STD_LOGIC; 
  signal dvm_main_curr_state_FFD2 : STD_LOGIC; 
  signal a_0_MC_D2_PT_1 : STD_LOGIC; 
  signal a_0_MC_D2 : STD_LOGIC; 
  signal N363_MC_Q : STD_LOGIC; 
  signal FOOBAR6_ctinst_7 : STD_LOGIC; 
  signal N363_MC_R_OR_PRLD : STD_LOGIC; 
  signal N363_MC_D : STD_LOGIC; 
  signal cclk_II_FCLK : STD_LOGIC; 
  signal FOOBAR6_ctinst_0 : STD_LOGIC; 
  signal FOOBAR6_ctinst_4 : STD_LOGIC; 
  signal reset_button : STD_LOGIC; 
  signal dvm_main_curr_state_FFD4_MC_Q : STD_LOGIC; 
  signal dvm_main_curr_state_FFD4_MC_R_OR_PRLD : STD_LOGIC; 
  signal dvm_main_curr_state_FFD4_MC_D : STD_LOGIC; 
  signal dvm_main_curr_state_FFD4_MC_D1 : STD_LOGIC; 
  signal dvm_N1718 : STD_LOGIC; 
  signal dvm_main_curr_state_FFD4_MC_D2_PT_0 : STD_LOGIC; 
  signal dvm_main_curr_state_FFD4_MC_D2_PT_1 : STD_LOGIC; 
  signal dvm_main_curr_state_FFD4_MC_D2 : STD_LOGIC; 
  signal dvm_main_curr_state_FFD3_MC_Q : STD_LOGIC; 
  signal dvm_main_curr_state_FFD3_MC_R_OR_PRLD : STD_LOGIC; 
  signal dvm_main_curr_state_FFD3_MC_D : STD_LOGIC; 
  signal dvm_main_curr_state_FFD3_MC_D1 : STD_LOGIC; 
  signal dvm_main_curr_state_FFD3_MC_D2_PT_0 : STD_LOGIC; 
  signal dvm_N1044 : STD_LOGIC; 
  signal dvm_main_curr_state_FFD3_MC_D2_PT_1 : STD_LOGIC; 
  signal dvm_main_curr_state_FFD3_MC_D2_PT_2 : STD_LOGIC; 
  signal dvm_main_curr_state_FFD3_MC_D2_PT_3 : STD_LOGIC; 
  signal dvm_main_curr_state_FFD3_MC_D2 : STD_LOGIC; 
  signal dvm_N1718_MC_Q : STD_LOGIC; 
  signal dvm_N1718_MC_D : STD_LOGIC; 
  signal dvm_N1718_MC_D1 : STD_LOGIC; 
  signal dvm_N1718_MC_D2_PT_0 : STD_LOGIC; 
  signal dvm_N1718_MC_D2_PT_1 : STD_LOGIC; 
  signal dvm_N1718_MC_D2 : STD_LOGIC; 
  signal dvm_main_curr_state_FFD1_MC_Q : STD_LOGIC; 
  signal dvm_main_curr_state_FFD1_MC_R_OR_PRLD : STD_LOGIC; 
  signal dvm_main_curr_state_FFD1_MC_D : STD_LOGIC; 
  signal dvm_main_curr_state_FFD1_MC_D1 : STD_LOGIC; 
  signal dvm_main_curr_state_FFD1_MC_D2_PT_0 : STD_LOGIC; 
  signal dvm_main_curr_state_FFD1_MC_D2_PT_1 : STD_LOGIC; 
  signal dvm_main_curr_state_FFD1_MC_D2_PT_2 : STD_LOGIC; 
  signal dvm_main_curr_state_FFD1_MC_D2_PT_3 : STD_LOGIC; 
  signal dvm_main_curr_state_FFD1_MC_D2_PT_4 : STD_LOGIC; 
  signal dvm_main_curr_state_FFD1_MC_D2 : STD_LOGIC; 
  signal N_PZ_450_MC_Q : STD_LOGIC; 
  signal N_PZ_450_MC_D : STD_LOGIC; 
  signal N_PZ_450_MC_D1_PT_0 : STD_LOGIC; 
  signal N_PZ_450_MC_D1 : STD_LOGIC; 
  signal N_PZ_450_MC_D2 : STD_LOGIC; 
  signal dvm_main_curr_state_FFD2_MC_Q : STD_LOGIC; 
  signal dvm_main_curr_state_FFD2_MC_R_OR_PRLD : STD_LOGIC; 
  signal dvm_main_curr_state_FFD2_MC_D : STD_LOGIC; 
  signal dvm_main_curr_state_FFD2_MC_D1 : STD_LOGIC; 
  signal dvm_main_curr_state_FFD2_MC_D2_PT_0 : STD_LOGIC; 
  signal dvm_main_curr_state_FFD2_MC_D2_PT_1 : STD_LOGIC; 
  signal dvm_wr_addr3_flag : STD_LOGIC; 
  signal dvm_wr_addr4_flag : STD_LOGIC; 
  signal dvm_wr_addr7_flag : STD_LOGIC; 
  signal dvm_wr_addr5_flag : STD_LOGIC; 
  signal dvm_wr_addr6_flag : STD_LOGIC; 
  signal dvm_wr_addr24_flag : STD_LOGIC; 
  signal dvm_main_curr_state_FFD2_MC_D2_PT_2 : STD_LOGIC; 
  signal dvm_dm_sng_ln0_flag : STD_LOGIC; 
  signal dvm_dm_sng_ln2_flag : STD_LOGIC; 
  signal dvm_dm_sng_ln1_flag : STD_LOGIC; 
  signal dvm_dm_sng_ln3_flag : STD_LOGIC; 
  signal dvm_dm_sng_ln4_flag : STD_LOGIC; 
  signal dvm_dm_sng_ln5_flag : STD_LOGIC; 
  signal dvm_dm_sng_ln6_flag : STD_LOGIC; 
  signal dvm_dm_sng_ln7_flag : STD_LOGIC; 
  signal dvm_main_curr_state_FFD2_MC_D2_PT_3 : STD_LOGIC; 
  signal dvm_main_curr_state_FFD2_MC_D2 : STD_LOGIC; 
  signal dvm_N1044_MC_Q : STD_LOGIC; 
  signal dvm_N1044_MC_D : STD_LOGIC; 
  signal dvm_N1044_MC_D1 : STD_LOGIC; 
  signal dvm_N1007 : STD_LOGIC; 
  signal dvm_N1011 : STD_LOGIC; 
  signal dvm_N1013 : STD_LOGIC; 
  signal sclk_MC_UIM : STD_LOGIC; 
  signal dvm_N374 : STD_LOGIC; 
  signal dvm_N377 : STD_LOGIC; 
  signal dvm_N1040 : STD_LOGIC; 
  signal dvm_N1044_MC_D2_PT_0 : STD_LOGIC; 
  signal dvm_N1044_MC_D2_PT_1 : STD_LOGIC; 
  signal dvm_N1044_MC_D2 : STD_LOGIC; 
  signal dvm_N1007_MC_Q : STD_LOGIC; 
  signal FOOBAR11_ctinst_1 : STD_LOGIC; 
  signal dvm_N1007_MC_R_OR_PRLD : STD_LOGIC; 
  signal dvm_N1007_MC_D : STD_LOGIC; 
  signal FOOBAR11_ctinst_4 : STD_LOGIC; 
  signal N825 : STD_LOGIC; 
  signal FOOBAR11_ctinst_0 : STD_LOGIC; 
  signal dvm_shift_curr_state_FFT1 : STD_LOGIC; 
  signal dvm_shift_curr_state_FFT2 : STD_LOGIC; 
  signal N825_MC_Q : STD_LOGIC; 
  signal N825_MC_D : STD_LOGIC; 
  signal N825_MC_D1 : STD_LOGIC; 
  signal sp_wen_II_UIM : STD_LOGIC; 
  signal N825_MC_D2_PT_0 : STD_LOGIC; 
  signal sp_cs1n_II_UIM : STD_LOGIC; 
  signal sp_cs0n_II_UIM : STD_LOGIC; 
  signal N825_MC_D2_PT_1 : STD_LOGIC; 
  signal N825_MC_D2 : STD_LOGIC; 
  signal dvm_shift_curr_state_FFT1_MC_Q : STD_LOGIC; 
  signal dvm_shift_curr_state_FFT1_MC_R_OR_PRLD : STD_LOGIC; 
  signal dvm_shift_curr_state_FFT1_MC_D : STD_LOGIC; 
  signal dvm_shift_curr_state_FFT1_MC_D1 : STD_LOGIC; 
  signal dvm_shift_curr_state_FFT1_MC_D2_PT_0 : STD_LOGIC; 
  signal dvm_shift_curr_state_FFT1_MC_D2_PT_1 : STD_LOGIC; 
  signal dvm_shift_curr_state_FFT1_MC_D2_PT_2 : STD_LOGIC; 
  signal dvm_shift_curr_state_FFT1_MC_D2_PT_3 : STD_LOGIC; 
  signal dvm_shift_curr_state_FFT1_MC_D2_PT_4 : STD_LOGIC; 
  signal N_PZ_570 : STD_LOGIC; 
  signal dvm_shift_curr_state_FFT1_MC_D2_PT_5 : STD_LOGIC; 
  signal dvm_shift_curr_state_FFT1_MC_D2 : STD_LOGIC; 
  signal dvm_shift_curr_state_FFT2_MC_Q : STD_LOGIC; 
  signal dvm_shift_curr_state_FFT2_MC_R_OR_PRLD : STD_LOGIC; 
  signal dvm_shift_curr_state_FFT2_MC_D : STD_LOGIC; 
  signal dvm_shift_curr_state_FFT2_MC_D1_PT_0 : STD_LOGIC; 
  signal dvm_shift_curr_state_FFT2_MC_D1 : STD_LOGIC; 
  signal dvm_shift_curr_state_FFT2_MC_D2 : STD_LOGIC; 
  signal dvm_shift_curr_state_FFT2_MC_D_TFF : STD_LOGIC; 
  signal dvm_N1040_MC_Q : STD_LOGIC; 
  signal dvm_N1040_MC_D : STD_LOGIC; 
  signal dvm_N1040_MC_D1_PT_0 : STD_LOGIC; 
  signal dvm_N1040_MC_D1 : STD_LOGIC; 
  signal dvm_N1040_MC_D2 : STD_LOGIC; 
  signal dvm_N1011_MC_Q : STD_LOGIC; 
  signal FOOBAR10_ctinst_1 : STD_LOGIC; 
  signal dvm_N1011_MC_R_OR_PRLD : STD_LOGIC; 
  signal dvm_N1011_MC_D : STD_LOGIC; 
  signal FOOBAR10_ctinst_0 : STD_LOGIC; 
  signal FOOBAR10_ctinst_4 : STD_LOGIC; 
  signal dvm_N1011_MC_D1_PT_0 : STD_LOGIC; 
  signal dvm_N1011_MC_D1 : STD_LOGIC; 
  signal dvm_N1011_MC_D2 : STD_LOGIC; 
  signal dvm_N1011_MC_D_TFF : STD_LOGIC; 
  signal dvm_N1013_MC_Q : STD_LOGIC; 
  signal dvm_N1013_MC_R_OR_PRLD : STD_LOGIC; 
  signal dvm_N1013_MC_D : STD_LOGIC; 
  signal dvm_N1013_MC_D1_PT_0 : STD_LOGIC; 
  signal dvm_N1013_MC_D1 : STD_LOGIC; 
  signal dvm_N1013_MC_D2 : STD_LOGIC; 
  signal dvm_N1013_MC_D_TFF : STD_LOGIC; 
  signal sclk_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal sclk_MC_Q : STD_LOGIC; 
  signal sclk_MC_D : STD_LOGIC; 
  signal sclk_MC_D1_PT_0 : STD_LOGIC; 
  signal sclk_MC_D1 : STD_LOGIC; 
  signal sclk_MC_D2 : STD_LOGIC; 
  signal dvm_N374_MC_Q : STD_LOGIC; 
  signal dvm_N374_MC_R_OR_PRLD : STD_LOGIC; 
  signal dvm_N374_MC_D : STD_LOGIC; 
  signal dvm_N374_MC_D1_PT_0 : STD_LOGIC; 
  signal dvm_N374_MC_D1 : STD_LOGIC; 
  signal dvm_N374_MC_D2 : STD_LOGIC; 
  signal dvm_N374_MC_D_TFF : STD_LOGIC; 
  signal dvm_N377_MC_Q : STD_LOGIC; 
  signal dvm_N377_MC_R_OR_PRLD : STD_LOGIC; 
  signal dvm_N377_MC_D : STD_LOGIC; 
  signal dvm_N377_MC_D1_PT_0 : STD_LOGIC; 
  signal dvm_N377_MC_D1 : STD_LOGIC; 
  signal dvm_N377_MC_D2 : STD_LOGIC; 
  signal dvm_N377_MC_D_TFF : STD_LOGIC; 
  signal dvm_dm_sng_ln0_flag_MC_Q : STD_LOGIC; 
  signal dvm_dm_sng_ln0_flag_MC_D : STD_LOGIC; 
  signal dvm_dm_sng_ln0_flag_MC_D1 : STD_LOGIC; 
  signal reset_adn_MC_UIM : STD_LOGIC; 
  signal dvm_dm_sng_ln0_flag_MC_D2_PT_0 : STD_LOGIC; 
  signal dvm_dm_num_0 : STD_LOGIC; 
  signal dvm_dm_num_1 : STD_LOGIC; 
  signal dvm_dm_num_2 : STD_LOGIC; 
  signal dvm_N2005 : STD_LOGIC; 
  signal dvm_dm_sng_ln0_flag_MC_D2_PT_1 : STD_LOGIC; 
  signal dvm_dm_sng_ln0_flag_MC_D2 : STD_LOGIC; 
  signal reset_adn_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal reset_adn_MC_Q : STD_LOGIC; 
  signal reset_adn_MC_D : STD_LOGIC; 
  signal reset_adn_MC_D1_PT_0 : STD_LOGIC; 
  signal reset_adn_MC_D1 : STD_LOGIC; 
  signal reset_adn_MC_D2 : STD_LOGIC; 
  signal dvm_dm_num_0_MC_Q : STD_LOGIC; 
  signal dvm_dm_num_0_MC_R_OR_PRLD : STD_LOGIC; 
  signal dvm_dm_num_0_MC_D : STD_LOGIC; 
  signal dvm_dm_num_0_MC_D1 : STD_LOGIC; 
  signal dvm_dm_num_0_MC_D2_PT_0 : STD_LOGIC; 
  signal dvm_dm_num_0_MC_D2_PT_1 : STD_LOGIC; 
  signal dvm_dm_num_0_MC_D2_PT_2 : STD_LOGIC; 
  signal dvm_dm_num_0_MC_D2_PT_3 : STD_LOGIC; 
  signal dvm_dm_num_0_MC_D2_PT_4 : STD_LOGIC; 
  signal dvm_dm_num_0_MC_D2_PT_5 : STD_LOGIC; 
  signal dvm_dm_num_0_MC_D2_PT_6 : STD_LOGIC; 
  signal dvm_dm_num_0_MC_D2 : STD_LOGIC; 
  signal dvm_dm_sng_ln1_flag_MC_Q : STD_LOGIC; 
  signal dvm_dm_sng_ln1_flag_MC_D : STD_LOGIC; 
  signal dvm_dm_sng_ln1_flag_MC_D1 : STD_LOGIC; 
  signal dvm_dm_sng_ln1_flag_MC_D2_PT_0 : STD_LOGIC; 
  signal dvm_N1955 : STD_LOGIC; 
  signal dvm_dm_sng_ln1_flag_MC_D2_PT_1 : STD_LOGIC; 
  signal dvm_dm_sng_ln1_flag_MC_D2 : STD_LOGIC; 
  signal dvm_dm_num_1_MC_Q : STD_LOGIC; 
  signal dvm_dm_num_1_MC_R_OR_PRLD : STD_LOGIC; 
  signal dvm_dm_num_1_MC_D : STD_LOGIC; 
  signal dvm_dm_num_1_MC_D1 : STD_LOGIC; 
  signal dvm_dm_num_1_MC_D2_PT_0 : STD_LOGIC; 
  signal dvm_dm_num_1_MC_D2_PT_1 : STD_LOGIC; 
  signal dvm_dm_num_1_MC_D2_PT_2 : STD_LOGIC; 
  signal dvm_dm_num_1_MC_D2_PT_3 : STD_LOGIC; 
  signal dvm_dm_num_1_MC_D2_PT_4 : STD_LOGIC; 
  signal N_PZ_479 : STD_LOGIC; 
  signal dvm_dm_num_1_MC_D2_PT_5 : STD_LOGIC; 
  signal dvm_dm_num_1_MC_D2 : STD_LOGIC; 
  signal dvm_dm_sng_ln2_flag_MC_Q : STD_LOGIC; 
  signal dvm_dm_sng_ln2_flag_MC_D : STD_LOGIC; 
  signal dvm_dm_sng_ln2_flag_MC_D1 : STD_LOGIC; 
  signal dvm_dm_sng_ln2_flag_MC_D2_PT_0 : STD_LOGIC; 
  signal dvm_N1868 : STD_LOGIC; 
  signal dvm_dm_sng_ln2_flag_MC_D2_PT_1 : STD_LOGIC; 
  signal dvm_dm_sng_ln2_flag_MC_D2 : STD_LOGIC; 
  signal dvm_dm_num_2_MC_Q : STD_LOGIC; 
  signal dvm_dm_num_2_MC_R_OR_PRLD : STD_LOGIC; 
  signal dvm_dm_num_2_MC_D : STD_LOGIC; 
  signal dvm_dm_num_2_MC_D1 : STD_LOGIC; 
  signal dvm_dm_num_2_MC_D2_PT_0 : STD_LOGIC; 
  signal dvm_dm_num_2_MC_D2_PT_1 : STD_LOGIC; 
  signal dvm_dm_num_2_MC_D2_PT_2 : STD_LOGIC; 
  signal dvm_dm_num_2_MC_D2_PT_3 : STD_LOGIC; 
  signal dvm_dm_num_2_MC_D2 : STD_LOGIC; 
  signal dvm_dm_sng_ln3_flag_MC_Q : STD_LOGIC; 
  signal dvm_dm_sng_ln3_flag_MC_D : STD_LOGIC; 
  signal dvm_dm_sng_ln3_flag_MC_D1 : STD_LOGIC; 
  signal dvm_dm_sng_ln3_flag_MC_D2_PT_0 : STD_LOGIC;