top_level.cxt

8 Channel Digital Volt Meter

  </MCMux>
  <DFlop Nm="FB1_9_FF">
   <FlopCon NNm="cclk" Port="CLK"/>
   <FlopCon NNm="UCT3" Port="RST"/>
   <FlopCon NNm="PT_GND" Port="PST"/>
   <FlopCon NNm="FB1_9_D" Port="D"/>
   <FlopCon NNm="FB1_9_Q" Port="Q"/>
  </DFlop>
  <Or Nm="FB1_9_OR">
   <OrCon NNm="FB1_PT6" Port="I"/>
   <OrCon NNm="FB1_PT7" Port="I"/>
   <OrCon NNm="FB1_PT8" Port="I"/>
   <OrCon NNm="FB1_PT9" Port="I"/>
   <OrCon NNm="FB1_9_D" Port="Z"/>
  </Or>
 </Mc>
 <Mc Nm="FB1_10">
  <FBMux Nm="FB1_10_N">
   <MuxCon NNm="FB1_10_N" Port="Z"/>
   <MuxCon NNm="FB1_10_Q" Port="I"/>
  </FBMux>
  <MCMux Nm="FB1_10_P">
   <MuxCon NNm="FB1_10_P" Port="Z"/>
   <MuxCon NNm="FB1_10_I" Port="I"/>
  </MCMux>
  <DFlop Nm="FB1_10_FF">
   <FlopCon NNm="cclk" Port="CLK"/>
   <FlopCon NNm="UCT3" Port="RST"/>
   <FlopCon NNm="PT_GND" Port="PST"/>
   <FlopCon NNm="FB1_10_D" Port="D"/>
   <FlopCon NNm="FB1_10_Q" Port="Q"/>
  </DFlop>
  <Or Nm="FB1_10_OR">
   <OrCon NNm="FB1_PT0" Port="I"/>
   <OrCon NNm="FB1_PT1" Port="I"/>
   <OrCon NNm="FB1_PT2" Port="I"/>
   <OrCon NNm="FB1_PT3" Port="I"/>
   <OrCon NNm="FB1_PT4" Port="I"/>
   <OrCon NNm="FB1_PT5" Port="I"/>
   <OrCon NNm="FB1_10_D" Port="Z"/>
  </Or>
 </Mc>
 <Mc Nm="FB1_11">
  <FBMux Nm="FB1_11_N">
   <MuxCon NNm="FB1_11_N" Port="Z"/>
   <MuxCon NNm="FB1_11_Q" Port="I"/>
  </FBMux>
  <MCMux Nm="FB1_11_P">
   <MuxCon NNm="FB1_11_P" Port="Z"/>
   <MuxCon NNm="FB1_11_I" Port="I"/>
  </MCMux>
  <DFlop Nm="FB1_11_FF">
   <FlopCon NNm="cclk" Port="CLK"/>
   <FlopCon NNm="UCT3" Port="RST"/>
   <FlopCon NNm="PT_GND" Port="PST"/>
   <FlopCon NNm="FB1_PT28" Port="D"/>
   <FlopCon NNm="FB1_11_Q" Port="Q"/>
  </DFlop>
 </Mc>
 <Mc Nm="FB1_12">
  <FBMux Nm="FB1_12_N">
   <MuxCon NNm="FB1_12_N" Port="Z"/>
   <MuxCon NNm="FB1_12_Q" Port="I"/>
  </FBMux>
  <MCMux Nm="FB1_12_P">
   <MuxCon NNm="FB1_12_P" Port="Z"/>
   <MuxCon NNm="FB1_12_I" Port="I"/>
  </MCMux>
  <InBuf Nm="FB1_12_I">
   <BufCon NNm="FB1_12_I" Port="Z"/>
   <BufCon NNm="sp_a&lt;20&gt;" Port="I"/>
  </InBuf>
  <DFlop Nm="FB1_12_FF">
   <FlopCon NNm="cclk" Port="CLK"/>
   <FlopCon NNm="UCT3" Port="RST"/>
   <FlopCon NNm="PT_GND" Port="PST"/>
   <FlopCon NNm="FB1_12_D" Port="D"/>
   <FlopCon NNm="FB1_12_Q" Port="Q"/>
  </DFlop>
  <Or Nm="FB1_12_OR">
   <OrCon NNm="FB1_PT47" Port="I"/>
   <OrCon NNm="FB1_PT16" Port="I"/>
   <OrCon NNm="FB1_12_D" Port="Z"/>
  </Or>
 </Mc>
 <Mc Nm="FB1_13">
  <FBMux Nm="FB1_13_N">
   <MuxCon NNm="FB1_13_N" Port="Z"/>
   <MuxCon NNm="FB1_PT32" Port="I"/>
  </FBMux>
  <MCMux Nm="FB1_13_P">
   <MuxCon NNm="FB1_13_P" Port="Z"/>
   <MuxCon NNm="FB1_13_I" Port="I"/>
  </MCMux>
  <InBuf Nm="FB1_13_I">
   <BufCon NNm="FB1_13_I" Port="Z"/>
   <BufCon NNm="sp_cs1n" Port="I"/>
  </InBuf>
 </Mc>
 <Mc Nm="FB1_14">
  <FBMux Nm="FB1_14_N">
   <MuxCon NNm="FB1_14_N" Port="Z"/>
   <MuxCon NNm="FB1_14_Q" Port="I"/>
  </FBMux>
  <MCMux Nm="FB1_14_P">
   <MuxCon NNm="FB1_14_P" Port="Z"/>
   <MuxCon NNm="FB1_14_I" Port="I"/>
  </MCMux>
  <InBuf Nm="FB1_14_I">
   <BufCon NNm="FB1_14_I" Port="Z"/>
   <BufCon NNm="sp_oen" Port="I"/>
  </InBuf>
  <DFlop Nm="FB1_14_FF">
   <FlopCon NNm="cclk" Port="CLK"/>
   <FlopCon NNm="UCT3" Port="RST"/>
   <FlopCon NNm="PT_GND" Port="PST"/>
   <FlopCon NNm="FB1_14_D" Port="D"/>
   <FlopCon NNm="FB1_14_Q" Port="Q"/>
  </DFlop>
  <Or Nm="FB1_14_OR">
   <OrCon NNm="FB1_PT43" Port="I"/>
   <OrCon NNm="FB1_PT44" Port="I"/>
   <OrCon NNm="FB1_PT45" Port="I"/>
   <OrCon NNm="FB1_PT46" Port="I"/>
   <OrCon NNm="FB1_14_D" Port="Z"/>
  </Or>
 </Mc>
 <Mc Nm="FB1_15">
  <FBMux Nm="FB1_15_N">
   <MuxCon NNm="FB1_15_N" Port="Z"/>
   <MuxCon NNm="FB1_15_Q" Port="I"/>
  </FBMux>
  <MCMux Nm="FB1_15_P">
   <MuxCon NNm="FB1_15_P" Port="Z"/>
   <MuxCon NNm="FB1_15_I" Port="I"/>
  </MCMux>
  <DFlop Nm="FB1_15_FF">
   <FlopCon NNm="cclk" Port="CLK"/>
   <FlopCon NNm="UCT3" Port="RST"/>
   <FlopCon NNm="PT_GND" Port="PST"/>
   <FlopCon NNm="FB1_15_D" Port="D"/>
   <FlopCon NNm="FB1_15_Q" Port="Q"/>
  </DFlop>
  <Or Nm="FB1_15_OR">
   <OrCon NNm="FB1_PT40" Port="I"/>
   <OrCon NNm="FB1_PT33" Port="I"/>
   <OrCon NNm="FB1_PT38" Port="I"/>
   <OrCon NNm="FB1_PT41" Port="I"/>
   <OrCon NNm="FB1_PT42" Port="I"/>
   <OrCon NNm="FB1_15_D" Port="Z"/>
  </Or>
 </Mc>
 <Mc Nm="FB1_16">
  <FBMux Nm="FB1_16_N">
   <MuxCon NNm="FB1_16_N" Port="Z"/>
   <MuxCon NNm="FB1_16_Q" Port="I"/>
  </FBMux>
  <MCMux Nm="FB1_16_P">
   <MuxCon NNm="FB1_16_P" Port="Z"/>
   <MuxCon NNm="FB1_16_I" Port="I"/>
  </MCMux>
  <DFlop Nm="FB1_16_FF">
   <FlopCon NNm="cclk" Port="CLK"/>
   <FlopCon NNm="UCT3" Port="RST"/>
   <FlopCon NNm="PT_GND" Port="PST"/>
   <FlopCon NNm="FB1_16_D" Port="D"/>
   <FlopCon NNm="FB1_16_Q" Port="Q"/>
  </DFlop>
  <Or Nm="FB1_16_OR">
   <OrCon NNm="FB1_PT36" Port="I"/>
   <OrCon NNm="FB1_PT33" Port="I"/>
   <OrCon NNm="FB1_PT37" Port="I"/>
   <OrCon NNm="FB1_PT38" Port="I"/>
   <OrCon NNm="FB1_PT39" Port="I"/>
   <OrCon NNm="FB1_16_D" Port="Z"/>
  </Or>
 </Mc>
</Lb>
<Lb Nm="FB2">
 <LbT Nm="FB2_PT0" PtT="CT">
  <LbTO NNm="FB2_PT0"/>
  <!-- dvm/wr_addr3_flag_n -->
  <LbTI NNm="FB2_11_N"/>
  <!-- reset_adn_n -->
  <LbTI NNm="FB8_4_N"/>
 </LbT>
 <LbT Nm="FB2_PT1" PtT="CT">
  <LbTO NNm="FB2_PT1"/>
  <!-- dvm/main_curr_state_FFD3_n -->
  <LbTI NNm="FB1_14_N"/>
  <!-- dvm/main_curr_state_FFD2_n -->
  <LbTI NNm="FB1_9_N"/>
  <!-- reset_adn_n -->
  <LbTI NNm="FB8_4_N"/>
  <!-- dvm/N1718_n -->
  <LbTI NNm="FB9_2_N"/>
 </LbT>
 <LbT Nm="FB2_PT2" PtT="CT">
  <LbTO NNm="FB2_PT2"/>
  <!-- dvm/wr_addr7_flag_n -->
  <LbTI NNm="FB2_10_N"/>
  <!-- reset_adn_n -->
  <LbTI NNm="FB8_4_N"/>
 </LbT>
 <LbT Nm="FB2_PT3" PtT="CT">
  <LbTO NNm="FB2_PT3"/>
  <!-- dvm/main_curr_state_FFD3_n -->
  <LbTI NNm="FB1_14_N"/>
  <!-- dvm/main_curr_state_FFD2_n -->
  <LbTI NNm="FB1_9_N"/>
  <!-- dvm/wr_addr3_flag_n -->
  <LbTI NNm="FB2_11_N"/>
  <!-- reset_adn_n -->
  <LbTI NNm="FB8_4_N"/>
  <!-- dvm/N1718_n -->
  <LbTI NNm="FB9_2_N"/>
 </LbT>
 <LbT Nm="FB2_PT4" PtT="CT">
  <LbTO NNm="FB2_PT4"/>
  <!-- dvm/main_curr_state_FFD3_n -->
  <LbTI NNm="FB1_14_N"/>
  <!-- dvm/main_curr_state_FFD2_n -->
  <LbTI NNm="FB1_9_N"/>
  <!-- dvm/wr_addr3_flag_n -->
  <LbTI NNm="FB2_11_N"/>
  <!-- dvm/wr_addr4_flag_n -->
  <LbTI NNm="FB2_9_N"/>
  <!-- dvm/wr_addr7_flag_n -->
  <LbTI NNm="FB2_10_N"/>
  <!-- dvm/N1718_n -->
  <LbTI NNm="FB9_2_N"/>
 </LbT>
 <LbT Nm="FB2_PT5" PtT="CT">
  <LbTO NNm="FB2_PT5"/>
  <!-- dvm/wr_addr4_flag_n -->
  <LbTI NNm="FB2_9_N"/>
  <!-- reset_adn_n -->
  <LbTI NNm="FB8_4_N"/>
  <!-- N_PZ_570_n -->
  <LbTI NNm="FB1_5_N"/>
 </LbT>
 <LbT Nm="FB2_PT6" PtT="CT">
  <LbTO NNm="FB2_PT6"/>
  <!-- dvm/wr_addr5_flag_n -->
  <LbTI NNm="FB2_8_N"/>
  <!-- reset_adn_n -->
  <LbTI NNm="FB8_4_N"/>
 </LbT>
 <LbT Nm="FB2_PT7" PtT="UCT">
  <LbTO NNm="FB2_PT7"/>
  <!-- sclk_n -->
  <LbTI NNm="FB6_12_N"/>
 </LbT>
 <LbT Nm="FB2_PT8" PtT="0">
  <LbTO NNm="FB2_PT8"/>
  <!-- dvm/main_curr_state_FFD3_n -->
  <LbTI NNm="FB1_14_N"/>
  <!-- dvm/main_curr_state_FFD2_n -->
  <LbTI NNm="FB1_9_N"/>
  <!-- dvm/wr_addr3_flag_n -->
  <LbTI NNm="FB2_11_N"/>
  <!-- dvm/wr_addr4_flag_n -->
  <LbTI NNm="FB2_9_N"/>
  <!-- dvm/wr_addr7_flag_n -->
  <LbTI NNm="FB2_10_N"/>
  <!-- reset_adn_n -->
  <LbTI NNm="FB8_4_N"/>
  <!-- dvm/N1718_n -->
  <LbTI NNm="FB9_2_N"/>
 </LbT>
 <LbT Nm="FB2_PT9" PtT="CLK">
  <LbTO NNm="FB2_PT9"/>
  <!-- dvm/wr_addr6_flag_n -->
  <LbTI NNm="FB2_7_N"/>
  <!-- reset_adn_n -->
  <LbTI NNm="FB8_4_N"/>
 </LbT>
 <LbT Nm="FB2_PT10" PtT="0">
  <LbTO NNm="FB2_PT10"/>
  <!-- d&lt;14&gt;_p -->
  <LbTI NNm="FB11_2_P"/>
 </LbT>
 <LbT Nm="FB2_PT11" PtT="CLK">
  <LbTO NNm="FB2_PT11"/>
  <!-- dvm/main_curr_state_FFD3_n -->
  <LbTI NNm="FB1_14_N"/>
  <!-- dvm/main_curr_state_FFD2_n -->
  <LbTI NNm="FB1_9_N"/>
  <!-- dvm/wr_addr3_flag_n -->
  <LbTI NNm="FB2_11_N"/>
  <!-- dvm/wr_addr4_flag_n -->
  <LbTI NNm="FB2_9_N"/>
  <!-- dvm/wr_addr5_flag_n -->
  <LbTI NNm="FB2_8_N"/>
  <!-- dvm/wr_addr7_flag_n -->
  <LbTI NNm="FB2_10_N"/>
  <!-- reset_adn_n -->
  <LbTI NNm="FB8_4_N"/>
  <!-- dvm/N1718_n -->
  <LbTI NNm="FB9_2_N"/>
 </LbT>
 <LbT Nm="FB2_PT12" PtT="0">
  <LbTO NNm="FB2_PT12"/>
  <!-- d&lt;13&gt;_p -->
  <LbTI NNm="FB11_12_P"/>
 </LbT>
 <LbT Nm="FB2_PT13" PtT="CLK">
  <LbTO NNm="FB2_PT13"/>
  <!-- dvm/wr_addr24_flag_n -->
  <LbTI NNm="FB2_6_N"/>
 </LbT>
 <LbT Nm="FB2_PT14" PtT="0">
  <LbTO NNm="FB2_PT14"/>
  <!-- d&lt;7&gt;_p -->
  <LbTI NNm="FB11_4_P"/>
 </LbT>
 <LbT Nm="FB2_PT15" PtT="CLK">
  <LbTO NNm="FB2_PT15"/>
  <!-- reset_adn_n -->
  <LbTI NNm="FB8_4_N"/>
  <!-- N_PZ_570_n -->
  <LbTI NNm="FB1_5_N"/>
 </LbT>
 <LbT Nm="FB2_PT16" PtT="0">
  <LbTO NNm="FB2_PT16"/>
  <!-- d&lt;6&gt;_p -->
  <LbTI NNm="FB11_1_P"/>
 </LbT>
 <LbT Nm="FB2_PT17" PtT="CLK">
  <LbTO NNm="FB2_PT17"/>
  <!-- dvm/wr_addr3_flag_n -->
  <LbTI NNm="FB2_11_N"/>
  <!-- dvm/wr_addr4_flag_n -->
  <LbTI NNm="FB2_9_N"/>
  <!-- dvm/wr_addr5_flag_n -->
  <LbTI NNm="FB2_8_N"/>
  <!-- dvm/wr_addr7_flag_n -->
  <LbTI NNm="FB2_10_N"/>
  <!-- dvm/wr_addr6_flag_n -->
  <LbTI NNm="FB2_7_N"/>
  <!-- N_PZ_570_n -->
  <LbTI NNm="FB1_5_N"/>
 </LbT>
 <LbT Nm="FB2_PT18" PtT="0">
  <LbTO NNm="FB2_PT18"/>
  <!-- dvm/main_curr_state_FFD3_n -->
  <LbTI NNm="FB1_14_N"/>
  <!-- dvm/main_curr_state_FFD2_n -->
  <LbTI NNm="FB1_9_N"/>
  <!-- dvm/wr_addr3_flag_n -->
  <LbTI NNm="FB2_11_N"/>
  <!-- dvm/wr_addr4_flag_n -->
  <LbTI NNm="FB2_9_N"/>
  <!-- dvm/wr_addr5_flag_n -->
  <LbTI NNm="FB2_8_N"/>
  <!-- dvm/wr_addr7_flag_n -->
  <LbTI NNm="FB2_10_N"/>
  <!-- dvm/wr_addr6_flag_n -->
  <LbTI NNm="FB2_7_N"/>
  <!-- dvm/wr_addr24_flag_n -->
  <LbTI NNm="FB2_6_N"/>
  <!-- dvm/N1718_n -->
  <LbTI NNm="FB9_2_N"/>
  <!-- dvm/shift_data/N133_n -->
  <LbTI NNm="FB11_10_N"/>
 </LbT>
 <LbT Nm="FB2_PT19" PtT="CLK">
  <LbTO NNm="FB2_PT19"/>
  <!-- dvm/main_curr_state_FFD4_n -->
  <LbTI NNm="FB1_12_N"/>
  <!-- dvm/main_curr_state_FFD1_n -->
  <LbTI NNm="FB3_11_N"/>
  <!-- dvm/main_curr_state_FFD3_n -->
  <LbTI NNm="FB1_14_N"/>
  <!-- dvm/main_curr_state_FFD2_n -->
  <LbTI NNm="FB1_9_N"/>
  <!-- dvm/wr_reg_num_0_n -->
  <LbTI NNm="FB1_16_N"/>
  <!-- dvm/wr_reg_num_1_n -->
  <LbTI NNm="FB1_15_N"/>
  <!-- dvm/wr_reg_num_2_n -->
  <LbTI NNm="FB1_6_N"/>
  <!-- dvm/N1718_n -->
  <LbTI NNm="FB9_2_N"/>
  <!-- dvm/shift_data/N133_n -->
  <LbTI NNm="FB11_10_N"/>
 </LbT>
 <LbT Nm="FB2_PT20" PtT="0">
  <LbTO NNm="FB2_PT20"/>
  <!-- dvm/main_curr_state_FFD4_n -->
  <LbTI NNm="FB1_12_N"/>
  <!-- dvm/main_curr_state_FFD1_n -->
  <LbTI NNm="FB3_11_N"/>
  <!-- dvm/main_curr_state_FFD3_n -->
  <LbTI NNm="FB1_14_N"/>
  <!-- dvm/main_curr_state_FFD2_n -->
  <LbTI NNm="FB1_9_N"/>
  <!-- dvm/wr_reg_num_0_n -->
  <LbTI NNm="FB1_16_N"/>
  <!-- dvm/wr_reg_num_1_n -->
  <LbTI NNm="FB1_15_N"/>
  <!-- dvm/wr_reg_num_2_n -->
  <LbTI NNm="FB1_6_N"/>
  <!-- dvm/N1718_n -->
  <LbTI NNm="FB9_2_N"/>
  <!-- dvm/shift_data/N133_n -->
  <LbTI NNm="FB11_10_N"/>
 </LbT>
 <LbT Nm="FB2_PT21" PtT="CLK">
  <LbTO NNm="FB2_PT21"/>
  <!-- dvm/main_curr_state_FFD4_n -->
  <LbTI NNm="FB1_12_N"/>
  <!-- dvm/main_curr_state_FFD1_n -->
  <LbTI NNm="FB3_11_N"/>
  <!-- dvm/main_curr_state_FFD3_n -->
  <LbTI NNm="FB1_14_N"/>
  <!-- dvm/main_curr_state_FFD2_n -->
  <LbTI NNm="FB1_9_N"/>
  <!-- dvm/wr_reg_num_0_n -->
  <LbTI NNm="FB1_16_N"/>
  <!-- dvm/wr_reg_num_1_n -->
  <LbTI NNm="FB1_15_N"/>
  <!-- dvm/wr_reg_num_2_n -->
  <LbTI NNm="FB1_6_N"/>
  <!-- dvm/N1718_n -->
  <LbTI NNm="FB9_2_N"/>
  <!-- dvm/shift_data/N133_n -->
  <LbTI NNm="FB11_10_N"/>
 </LbT>
 <LbT Nm="FB2_PT22" PtT="0">
  <LbTO NNm="FB2_PT22"/>
  <!-- dvm/N5446_n -->
  <LbTI NNm="FB5_7_N"/>
  <!-- dvm/N1718_n -->
  <LbTI NNm="FB9_2_N"/>
  <!-- dvm/shift_data/N133_n -->
  <LbTI NNm="FB11_10_N"/>
 </LbT>
 <LbT Nm="FB2_PT23" PtT="CLK">
  <LbTO NNm="FB2_PT23"/>
  <!-- dvm/N5445_n -->
  <LbTI NNm="FB2_1_N"/>
  <!-- dvm/shift_data/N133_n -->
  <LbTI NNm="FB11_10_N"/>
 </LbT>
 <LbT Nm="FB2_PT30" PtT="0">
  <LbTO NNm="FB2_PT30"/>
  <!-- d&lt;11&gt;_p -->
  <LbTI NNm="FB11_15_P"/>
 </LbT>
 <LbT Nm="FB2_PT32" PtT="0">
  <LbTO NNm="FB2_PT32"/>
  <!-- d&lt;12&gt;_p -->
  <LbTI NNm="FB11_13_P"/>
 </LbT>
 <LbT Nm="FB2_PT34" PtT="0">
  <LbTO NNm="FB2_PT34"/>
  <!-- d&lt;4&gt;_p -->
  <LbTI NNm="FB11_16_P"/>
 </LbT>
 <LbT Nm="FB2_PT36" PtT="0">
  <LbTO NNm="FB2_PT36"/>