top_level.ph0

来自「8 Channel Digital Volt Meter」· PH0 代码 · 共 1,940 行 · 第 1/5 页

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 	dvm/N5442  node istype 'reg';  " 2 pt.
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 	dvm/N989  node ;  " 2 pt.
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 	dvm/addr_set  node istype 'reg';  " 2 pt.
 	dvm/cnt5/N100  node ;  " 1 pt.
 	dvm/cnt5/N104  node ;  " 1 pt.
 	dvm/cnt5/N52  node ;  " 1 pt.
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 	dvm/cnt5/N96  node ;  " 1 pt.
 	dvm/dm_num_0  node istype 'reg';  " 6 pt.
 	dvm/dm_num_1  node istype 'reg';  " 6 pt.
 	dvm/dm_num_2  node istype 'reg';  " 6 pt.
 	dvm/dm_sng_ln0_flag  node istype 'reg';  " 3 pt.
 	dvm/dm_sng_ln1_flag  node istype 'reg';  " 3 pt.
 	dvm/dm_sng_ln2_flag  node istype 'reg';  " 3 pt.
 	dvm/dm_sng_ln3_flag  node istype 'reg';  " 3 pt.
 	dvm/dm_sng_ln4_flag  node istype 'reg';  " 3 pt.
 	dvm/dm_sng_ln5_flag  node istype 'reg';  " 3 pt.
 	dvm/dm_sng_ln6_flag  node istype 'reg';  " 3 pt.
 	dvm/dm_sng_ln7_flag  node istype 'reg';  " 3 pt.
 	dvm/main_curr_state_FFD1  node istype 'reg';  " 1 pt.
 	dvm/main_curr_state_FFD2  node istype 'reg';  " 3 pt.
 	dvm/main_curr_state_FFD3  node istype 'reg';  " 2 pt.
 	dvm/main_curr_state_FFD4  node istype 'reg';  " 1 pt.
 	dvm/shift_curr_state_FFT1  node istype 'reg';  " 1 pt.
 	dvm/shift_curr_state_FFT2  node istype 'reg';  " 1 pt.
 	dvm/shift_data/N102  node ;  " 1 pt.
 	dvm/shift_data/N108  node ;  " 1 pt.
 	dvm/shift_data/N113  node ;  " 1 pt.
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 	dvm/shift_data/N80  node ;  " 1 pt.
 	dvm/shift_data/N86  node ;  " 1 pt.
 	dvm/shift_data/N91  node ;  " 1 pt.
 	dvm/shift_data/N97  node ;  " 1 pt.
 	dvm/wr_addr24_flag  node istype 'reg';  " 5 pt.
 	dvm/wr_addr3_flag  node istype 'reg';  " 2 pt.
 	dvm/wr_addr4_flag  node istype 'reg';  " 3 pt.
 	dvm/wr_addr5_flag  node istype 'reg';  " 2 pt.
 	dvm/wr_addr6_flag  node istype 'reg';  " 5 pt.
 	dvm/wr_addr7_flag  node istype 'reg';  " 3 pt.
 	dvm/wr_reg_num_0  node istype 'reg';  " 5 pt.
 	dvm/wr_reg_num_1  node istype 'reg';  " 5 pt.
 	dvm/wr_reg_num_2  node istype 'reg';  " 6 pt.
 	reset_button  node K4 istype 'reg';  " 2 pt.
 

xpla property 'USER_SLEW_RATE sp_d<10> sp_d<11> sp_d<12> sp_d<13> sp_d<14> sp_d<15> sp_d<8> 
	sp_d<9> sp_d<0> sp_d<1> sp_d<2> sp_d<3> sp_d<4> sp_d<5> sp_d<6> sp_d<7> reset_adn sclk d<0> d<10> 
	d<11> d<12> d<13> d<14> d<15> d<1> d<2> d<3> d<4> d<5> d<6> d<7> d<8> d<9> din io13 a<0> a<10> a<11> 
	a<12> a<13> a<14> a<15> a<16> a<17> a<18> a<19> a<1> a<20> a<21> a<22> a<2> a<3> a<4> a<5> a<6> a<7> 
	a<8> a<9> oen rwn ad_chip2_enn chip3_en busy_test sram_cs1n convert flash_cs0n flash_wr_protect 
	led1_sel led2_sel led3_sel led4_sel reset_memn osc_cntrl rise_fall sp_a_0 sram_low_byten sram_upper_byten 
	'; 
EQUATIONS 

 N216 = dvm/main_curr_state_FFD3
      # !dvm/main_curr_state_FFD2
      # dvm/main_curr_state_FFD4
      # !dvm/main_curr_state_FFD1;		"--- [PT=4, FI=4, LVL=1] ---
 N248 = sp_d<9>.PIN
      # sp_d<8>.PIN
      # sp_d<15>.PIN
      # sp_d<14>.PIN
      # sp_d<13>.PIN
      # sp_d<12>.PIN
      # sp_d<11>.PIN
      # sp_d<10>.PIN;		"--- [PT=8, FI=8, LVL=1] ---
 N266 = sp_d<7>.PIN
      # sp_d<6>.PIN
      # sp_d<5>.PIN
      # sp_d<4>.PIN
      # sp_d<3>.PIN
      # sp_d<2>.PIN
      # sp_d<1>.PIN
      # sp_d<0>.PIN;		"--- [PT=8, FI=8, LVL=1] ---
 N269 = !N348
      # N248
      # N266;		"--- [PT=3, FI=3, LVL=3] ---
 N282 = sp_d<10>.PIN & sp_d<11>.PIN & sp_d<12>.PIN & sp_d<13>.PIN & 
    sp_d<14>.PIN & sp_d<15>.PIN & sp_d<8>.PIN & sp_d<9>.PIN
    ;		"--- [PT=1, FI=8, LVL=1] ---
 N292 = sp_d<0>.PIN & sp_d<1>.PIN & sp_d<2>.PIN & sp_d<3>.PIN & sp_d<4>.PIN & 
    sp_d<5>.PIN & sp_d<6>.PIN & sp_d<7>.PIN;		"--- [PT=1, FI=8, LVL=1] ---
 N310 = sp_a<9>
      # sp_a<8>
      # sp_a<7>
      # sp_a<14>
      # sp_a<13>
      # sp_a<12>
      # sp_a<11>
      # sp_a<10>;		"--- [PT=8, FI=8, LVL=1] ---
 N326 = sp_a<1> & sp_a<2> & sp_a<3> & sp_a<4> & sp_a<5> & !sp_a<23> & !sp_a<6>
    ;		"--- [PT=1, FI=7, LVL=1] ---