top_level.prt

8 Channel Digital Volt Meter

Setting sync clock limit to 999.
Gct[0] comes from: block 1's CT7 (pt 120)
Gct[1] comes from: block 3's CT7 (pt 5308)
Gct[2] comes from: block 5's CT7 (pt 5040)
Gct[3] comes from: block 5's CT7 (pt 5040)

Pre-assignments saved.

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|  P a r t i t i o n i n g . . .  , Seed = 0, Approach = 0, state = 1, GrpAlg=0  |
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Check Pin-locking? Yes (Approach = -1); Timing-driven partition? No

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|  P a r t i t i o n    S u c c e e d  |
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0 Group(s)

ClkInput[1]: cclk(D11, sclk) 
GOE: 5308
GPST: 5040
GRST: 5040
GACLK: 120
----------------- B l o c k 0 ------------------
PLApt(48/48), Fanin(38/38), Clk(1/2), Bct(0/8), Pin(8/10), Mcell(13/16), FbNand(0/0)
PLApts[48/48] 44 176 143 165 264 253 242 286 177 111 375 243 287 232 288 167 112 168 113 278 234 157 257 279 
              246 235 247 225 115 5 94 116 403 271 249 238 162 404 239 118 405 163 240 229 164 241 175 406
Fanins[38] N_PZ_450.n N_PZ_479.n N_PZ_570.n dvm/N1007.n dvm/N1011.n dvm/N1013.n dvm/N1040.n dvm/N1044.n 
           dvm/N1718.n dvm/N374.n dvm/N377.n dvm/N5448.n dvm/N5449.n dvm/dm_sng_ln0_flag.n 
           dvm/dm_sng_ln1_flag.n dvm/dm_sng_ln2_flag.n dvm/dm_sng_ln3_flag.n dvm/dm_sng_ln4_flag.n 
           dvm/dm_sng_ln5_flag.n dvm/dm_sng_ln6_flag.n dvm/dm_sng_ln7_flag.n dvm/main_curr_state_FFD1.n 
           dvm/main_curr_state_FFD2.n dvm/main_curr_state_FFD3.n dvm/main_curr_state_FFD4.n 
           dvm/shift_curr_state_FFT1.n dvm/shift_curr_state_FFT2.n dvm/shift_data/N133.n dvm/wr_addr24_flag.n 
           dvm/wr_addr3_flag.n dvm/wr_addr4_flag.n dvm/wr_addr5_flag.n dvm/wr_addr6_flag.n 
           dvm/wr_addr7_flag.n dvm/wr_reg_num_0.n dvm/wr_reg_num_1.n dvm/wr_reg_num_2.n d<15>.p
clk[1/1] cclk 
BCTpts[0] 
Signal[20] [sp_d<15>(283),sp_d<15>(F15)] [sp_a<10>(F17)] [sp_a<14>(E18)] [sp_a<19>(E19)] [sp_a<20>(F19)]  
           [sp_cs1n(G16)] [sp_oen(G17)] [sp_wen(F18)] [dvm/shift_curr_state_FFT2(291)]  
           [dvm/shift_curr_state_FFT1(290)] [dvm/main_curr_state_FFD2(289)] [dvm/N5449(288)]  
           [dvm/N5448(287)] [dvm/wr_reg_num_2(286)] [dvm/wr_reg_num_0(296)] [dvm/wr_reg_num_1(295)]  
           [dvm/main_curr_state_FFD3(294)] [N_PZ_623(293)] [dvm/main_curr_state_FFD4(292)] [N_PZ_570(285)] 
FbNand[ 0] 
----------------- B l o c k 1 ------------------
PLApt(29/48), Fanin(29/38), Clk(1/2), Bct(1/8), Pin(10/10), Mcell(16/16), FbNand(0/0)
PLApts[29/29] 120 275 264 407 254 408 166 133 12 409 134 13 135 14 268 136 15 104 170 171 6 172 7 173 19 8 
              262 20 263
Fanins[29] reset_adn.n sclk.n N_PZ_570.n dvm/N1718.n dvm/N5445.n dvm/N5446.n dvm/main_curr_state_FFD1.n 
           dvm/main_curr_state_FFD2.n dvm/main_curr_state_FFD3.n dvm/main_curr_state_FFD4.n 
           dvm/shift_data/N133.n dvm/wr_addr24_flag.n dvm/wr_addr3_flag.n dvm/wr_addr4_flag.n 
           dvm/wr_addr5_flag.n dvm/wr_addr6_flag.n dvm/wr_addr7_flag.n dvm/wr_reg_num_0.n dvm/wr_reg_num_1.n 
           dvm/wr_reg_num_2.n d<11>.p d<12>.p d<13>.p d<14>.p d<3>.p d<4>.p d<5>.p d<6>.p d<7>.p
clk[1/1] cclk 
BCTpts[1] ct7:120 
Signal[17] [sp_d<11>(308),sp_d<11>(C16)] [sp_d<12>(309),sp_d<12>(A16)] [sp_d<13>(299),sp_d<13>(B17)]  
           [sp_d<14>(298),sp_d<14>(B18)] [sp_d<3>(311),sp_d<3>(D15)] [sp_d<4>(310),sp_d<4>(E15)]  
           [sp_d<5>(312),sp_d<5>(A15)] [sp_d<6>(301),sp_d<6>(A17)] [sp_d<7>(300),sp_d<7>(A18)]  
           [sp_cs0n(B19)] [dvm/wr_addr3_flag(307)] [dvm/wr_addr7_flag(306)] [dvm/wr_addr4_flag(305)]  
           [dvm/wr_addr5_flag(304)] [dvm/wr_addr6_flag(303)] [dvm/wr_addr24_flag(302)] [dvm/N5445(297)] 
FbNand[ 0] 
----------------- B l o c k 2 ------------------
PLApt(48/48), Fanin(33/38), Clk(1/2), Bct(0/8), Pin(8/10), Mcell(7/16), FbNand(0/0)
PLApts[48/48] 140 374 154 354 156 46 157 355 311 410 223 290 356 312 158 181 148 137 313 291 159 357 347 292 
              160 314 182 149 138 359 348 315 183 161 150 139 293 360 316 349 151 350 317 372 152 174 284 285
Fanins[33] reset_adn.n N363.n N473.n N513.n N523.n N533.n N543.n N553.n N_PZ_450.n N_PZ_452.n N_PZ_469.n 
           N_PZ_479.n N_PZ_579.n N_PZ_623.n dvm/N1044.n dvm/N1718.n dvm/N461.n dvm/addr_set.n dvm/dm_num_0.n 
           dvm/dm_num_1.n dvm/dm_num_2.n dvm/dm_sng_ln0_flag.n dvm/dm_sng_ln1_flag.n dvm/dm_sng_ln2_flag.n 
           dvm/dm_sng_ln3_flag.n dvm/dm_sng_ln4_flag.n dvm/dm_sng_ln5_flag.n dvm/dm_sng_ln6_flag.n 
           dvm/dm_sng_ln7_flag.n dvm/main_curr_state_FFD1.n dvm/main_curr_state_FFD2.n 
           dvm/main_curr_state_FFD3.n dvm/main_curr_state_FFD4.n
clk[1/1] cclk 
BCTpts[0] 
Signal[15] [sp_a<11>(H17)] [sp_a<15>(K18)] [sp_a<16>(H19)] [sp_a<17>(L16)] [sp_a<21>(H18)] [sp_a<22>(J18)]  
           [sp_a<8>(K17)] [sp_a<9>(J17)] [dvm/main_curr_state_FFD1(323)] [dvm/addr_set(322)] [N523(321)]  
           [N533(320)] [N543(319)] [N_PZ_469(318)] [N553(328)] 
FbNand[ 0] 
----------------- B l o c k 3 ------------------
PLApt(27/48), Fanin(32/38), Clk(0/2), Bct(4/8), Pin(9/10), Mcell(16/16), FbNand(0/0)
PLApts[27/27] 5141 93 91 5308 33 198 55 89 56 57 25 190 58 26 191 59 192 60 49 39 41 184 31 42 185 32 197
Fanins[32] N624.n N634.n N694.n N704.n N714.n N764.n N774.n N813.n N825.n N_PZ_450.n 
           dvm/main_curr_state_FFD1.n dvm/main_curr_state_FFD2.n dvm/main_curr_state_FFD3.n 
           dvm/main_curr_state_FFD4.n reset_button.n sp_d<0>.p sp_d<10>.p sp_d<11>.p sp_d<12>.p sp_d<13>.p 
           sp_d<14>.p sp_d<15>.p sp_d<1>.p sp_d<2>.p sp_d<3>.p sp_d<4>.p sp_d<5>.p sp_d<6>.p sp_d<7>.p 
           sp_d<8>.p sp_d<9>.p sp_oen.p
clk[0/0] 
BCTpts[4] ct0:5141 ct1:93 ct4:91 ct7:5308 
Signal[16] [d<0>(331),d<0>(A14)] [d<10>(343),d<10>(B12)] [d<1>(333),d<1>(B13)] [d<2>(344),d<2>(D12)]  
           [d<3>(341),d<3>(A12)] [d<8>(332),d<8>(C13)] [d<9>(340),d<9>(A13)] [oen(330),oen(D14)]  
           [flash_cs0n(329),flash_cs0n(E14)] [N_PZ_550(342)] [N634(339)] [N644(338)] [N694(337)] [N704(336)]  
           [N714(335)] [N724(334)] 
FbNand[ 0] 
----------------- B l o c k 4 ------------------
PLApt(48/48), Fanin(35/38), Clk(1/2), Bct(0/8), Pin(7/10), Mcell(9/16), FbNand(0/0)
PLApts[48/48] 264 110 276 254 265 155 144 266 277 255 244 178 145 267 256 245 179 146 48 411 147 180 269 236 
              412 258 237 270 248 259 105 260 106 261 250 272 107 371 262 273 251 108 274 263 252 153 373 109
Fanins[35] N_PZ_479.n N_PZ_623.n dvm/N1718.n dvm/N5442.n dvm/N5443.n dvm/N5444.n dvm/N5445.n dvm/N5446.n 
           dvm/N5447.n dvm/N5448.n dvm/dm_num_0.n dvm/dm_num_1.n dvm/dm_num_2.n dvm/dm_sng_ln0_flag.n 
           dvm/dm_sng_ln1_flag.n dvm/dm_sng_ln2_flag.n dvm/dm_sng_ln3_flag.n dvm/dm_sng_ln4_flag.n 
           dvm/dm_sng_ln5_flag.n dvm/dm_sng_ln6_flag.n dvm/dm_sng_ln7_flag.n dvm/main_curr_state_FFD1.n 
           dvm/main_curr_state_FFD2.n dvm/main_curr_state_FFD3.n dvm/main_curr_state_FFD4.n 
           dvm/shift_data/N133.n dvm/wr_addr24_flag.n dvm/wr_addr3_flag.n dvm/wr_addr4_flag.n 
           dvm/wr_addr5_flag.n dvm/wr_addr6_flag.n dvm/wr_addr7_flag.n dvm/wr_reg_num_0.n dvm/wr_reg_num_1.n 
           dvm/wr_reg_num_2.n
clk[1/1] cclk 
BCTpts[0] 
Signal[16] [sp_a<12>(M18)] [sp_a<13>(L17)] [sp_a<18>(M17)] [sp_a<23>(L18)] [sp_a<4>(N16)] [sp_a<5>(M16)]  
           [sp_a<7>(N18)] [dvm/dm_num_2(347)] [dvm/dm_num_1(355)] [dvm/dm_num_0(354)] [dvm/N5442(353)]  
           [dvm/N5447(352)] [dvm/N5446(351)] [dvm/N5443(350)] [dvm/N5444(360)] [N_PZ_450(359)] 
FbNand[ 0] 
----------------- B l o c k 5 ------------------
PLApt(42/48), Fanin(31/38), Clk(1/2), Bct(3/8), Pin(6/10), Mcell(16/16), FbNand(0/0)
PLApts[42/42] 362 93 91 5040 233 363 330 319 352 364 331 320 353 376 321 365 366 333 377 323 367 169 114 379 
              324 368 280 369 358 281 381 326 282 370 117 382 283 383 328 361 351 318
Fanins[31] N363.n N373.n N383.n N393.n N403.n N473.n N513.n N523.n N533.n N543.n N553.n N563.n N573.n N583.n 
           N_PZ_452.n N_PZ_469.n N_PZ_579.n N_PZ_594.n N_PZ_595.n dvm/N1040.n dvm/N1044.n dvm/N1718.n 
           dvm/N461.n dvm/N5442.n dvm/main_curr_state_FFD1.n dvm/main_curr_state_FFD2.n 
           dvm/main_curr_state_FFD3.n dvm/main_curr_state_FFD4.n dvm/shift_curr_state_FFT1.n 
           dvm/shift_curr_state_FFT2.n reset_button.n
clk[1/1] cclk 
BCTpts[3] ct0:93 ct4:91 ct7:5040 
Signal[18] [din(363),din(W11)] [ad_chip2_enn(361),ad_chip2_enn(U10)] [sclk(372),sclk(W12)]  
           [osc_cntrl(375),osc_cntrl(V13)] [rise_fall(364),rise_fall(U11)] [N_PZ_594(362),N624,dout(T10)]  
           [N363(371)] [N473(370)] [N513(369)] [N563(368)] [N573(367)] [N583(366)] [N373(376)] [N383(374)]  
           [N393(373)] [N403(365)] 
FbNand[ 0] 
----------------- B l o c k 6 ------------------
PLApt(30/48), Fanin(31/38), Clk(1/2), Bct(2/8), Pin(6/10), Mcell(16/16), FbNand(0/0)
PLApts[30/30] 93 91 297 34 298 35 299 300 301 125 27 302 126 28 413 303 127 17 29 304 30 294 305 129 306 295