top_level.ph2

8 Channel Digital Volt Meter

" XPLAOPT Version 9.99.99.99
" Created on Tue Jan 29 11:16:58 2002
" 171 Mcells, 15 FbNand, 434 PLApts, 9 Levels
" XPLAOPT -run f -it b -i top_level.blx -dev XCR3256XL-7CS280 -reg -xor a -mode 
"         1 -th 28 -fi 32 -bfi 38 -pre keep -fbn 0 -unused ground -terminate pullup 
MODULE top_level

	a<0>  pin T5 ;  " 2 pt.
 	a<10>  pin V5 ;  " 2 pt.
 	a<11>  pin W5 ;  " 2 pt.
 	a<12>  pin W4 ;  " 2 pt.
 	a<13>  pin W3 ;  " 2 pt.
 	a<14>  pin U6 ;  " 2 pt.
 	a<15>  pin T6 ;  " 2 pt.
 	a<16>  pin R6 ;  " 2 pt.
 	a<17>  pin W7 ;  " 2 pt.
 	a<18>  pin G1 ;  " 2 pt.
 	a<19>  pin U5 ;  " 2 pt.
 	a<1>  pin W10 ;  " 2 pt.
 	a<20>  pin U4 ;  " 2 pt.
 	a<21>  pin G2 ;  " 2 pt.
 	a<22>  pin G4 ;  " 2 pt.
 	a<2>  pin T9 ;  " 2 pt.
 	a<3>  pin U9 ;  " 2 pt.
 	a<4>  pin T8 ;  " 2 pt.
 	a<5>  pin V7 ;  " 2 pt.
 	a<6>  pin U7 ;  " 2 pt.
 	a<7>  pin T7 ;  " 2 pt.
 	a<8>  pin V6 ;  " 2 pt.
 	a<9>  pin W6 ;  " 2 pt.
 	ad_chip2_enn  pin U10 ;  " 1 pt.
 	busy  pin T14 ; 
 	busy_test  pin E1 ;  " 1 pt.
 	cclk  pin D11 ; 
 	chip3_en  pin M3 ;  " 1 pt.
 	convert  pin W14 ;  " 0 pt.
 	d<0>  pin A14 ;  " 2 pt.
 	d<10>  pin B12 ;  " 2 pt.
 	d<11>  pin D10 ;  " 2 pt.
 	d<12>  pin C9 ;  " 2 pt.
 	d<13>  pin B8 ;  " 2 pt.
 	d<14>  pin C7 ;  " 2 pt.
 	d<15>  pin B7 ;  " 2 pt.
 	d<1>  pin B13 ;  " 2 pt.
 	d<2>  pin D12 ;  " 2 pt.
 	d<3>  pin A12 ;  " 2 pt.
 	d<4>  pin C10 ;  " 2 pt.
 	d<5>  pin C8 ;  " 2 pt.
 	d<6>  pin D7 ;  " 2 pt.
 	d<7>  pin A7 ;  " 2 pt.
 	d<8>  pin C13 ;  " 2 pt.
 	d<9>  pin A13 ;  " 2 pt.
 	din  pin W11 ;  " 1 pt.
 	dout  pin T10 ; 
 	flash_cs0n  pin E14 ;  " 1 pt.
 	flash_wr_protect  pin H2 ;  " 1 pt.
 	io13  pin E2 ;  " 3 pt.
 	led1_sel  pin G3 ;  " 1 pt.
 	led2_sel  pin F4 ;  " 1 pt.
 	led3_sel  pin F3 ;  " 1 pt.
 	led4_sel  pin F5 ;  " 1 pt.
 	oen  pin D14 ;  " 1 pt.
 	osc_cntrl  pin V13 ;  " 1 pt.
 	reset_adn  pin R14 ;  " 1 pt.
 	reset_memn  pin T13 ;  " 1 pt.
 	rise_fall  pin U11 ;  " 1 pt.
 	rwn  pin J2 ;  " 3 pt.
 	sclk  pin W12 ;  " 1 pt.
 	sp_a<10>  pin F17 ; 
 	sp_a<11>  pin H17 ; 
 	sp_a<12>  pin M18 ; 
 	sp_a<13>  pin L17 ; 
 	sp_a<14>  pin E18 ; 
 	sp_a<15>  pin K18 ; 
 	sp_a<16>  pin H19 ; 
 	sp_a<17>  pin L16 ; 
 	sp_a<18>  pin M17 ; 
 	sp_a<19>  pin E19 ; 
 	sp_a<1>  pin T17 ; 
 	sp_a<20>  pin F19 ; 
 	sp_a<21>  pin H18 ; 
 	sp_a<22>  pin J18 ; 
 	sp_a<23>  pin L18 ; 
 	sp_a<2>  pin R16 ; 
 	sp_a<3>  pin R17 ; 
 	sp_a<4>  pin N16 ; 
 	sp_a<5>  pin M16 ; 
 	sp_a<6>  pin R19 ; 
 	sp_a<7>  pin N18 ; 
 	sp_a<8>  pin K17 ; 
 	sp_a<9>  pin J17 ; 
 	sp_a_0  pin U19 ;  " 0 pt.
 	sp_cs0n  pin B19 ; 
 	sp_cs1n  pin G16 ; 
 	sp_d<0>  pin V16 ;  " 1 pt.
 	sp_d<10>  pin U15 ;  " 1 pt.
 	sp_d<11>  pin C16 ;  " 1 pt.
 	sp_d<12>  pin A16 ;  " 1 pt.
 	sp_d<13>  pin B17 ;  " 1 pt.
 	sp_d<14>  pin B18 ;  " 1 pt.
 	sp_d<15>  pin F15 ;  " 1 pt.
 	sp_d<1>  pin W15 ;  " 1 pt.
 	sp_d<2>  pin T15 ;  " 1 pt.
 	sp_d<3>  pin D15 ;  " 1 pt.
 	sp_d<4>  pin E15 ;  " 1 pt.
 	sp_d<5>  pin A15 ;  " 1 pt.
 	sp_d<6>  pin A17 ;  " 1 pt.
 	sp_d<7>  pin A18 ;  " 1 pt.
 	sp_d<8>  pin V15 ;  " 1 pt.
 	sp_d<9>  pin T16 ;  " 1 pt.
 	sp_oen  pin G17 ; 
 	sp_wen  pin F18 ; 
 	sram_cs1n  pin K2 ;  " 3 pt.
 	sram_low_byten  pin K3 ;  " 0 pt.
 	sram_upper_byten  pin J3 ;  " 0 pt.
 

	N363  node ;  " 3 pt.
 	N373  node ;  " 3 pt.
 	N383  node ;  " 2 pt.
 	N393  node ;  " 2 pt.
 	N403  node ;  " 3 pt.
 	N413  node ;  " 2 pt.
 	N423  node ;  " 2 pt.
 	N433  node ;  " 3 pt.
 	N443  node ;  " 4 pt.
 	N453  node ;  " 5 pt.
 	N463  node ;  " 2 pt.
 	N473  node ;  " 4 pt.
 	N483  node ;  " 2 pt.
 	N493  node ;  " 3 pt.
 	N503  node ;  " 4 pt.
 	N513  node ;  " 5 pt.
 	N523  node ;  " 14 pt.
 	N533  node ;  " 11 pt.
 	N543  node ;  " 5 pt.
 	N553  node ;  " 4 pt.
 	N563  node ;  " 5 pt.
 	N573  node ;  " 2 pt.
 	N583  node ;  " 2 pt.
 	N624  node ;  " 1 pt.
 	N634  node ;  " 1 pt.
 	N644  node ;  " 1 pt.
 	N654  node ;  " 1 pt.
 	N664  node ;  " 1 pt.
 	N674  node ;  " 1 pt.
 	N684  node ;  " 1 pt.
 	N694  node ;  " 1 pt.
 	N704  node ;  " 1 pt.
 	N714  node ;  " 1 pt.
 	N724  node ;  " 1 pt.
 	N734  node ;  " 1 pt.
 	N744  node ;  " 1 pt.
 	N754  node ;  " 1 pt.
 	N764  node ;  " 1 pt.
 	N774  node ;  " 1 pt.
 	N813  node ;  " 2 pt.
 	N825  node ;  " 2 pt.
 	N_PZ_445  node istype 'collapse';  " 4 pt.
 	N_PZ_450  node istype 'collapse';  " 1 pt.
 	N_PZ_452  node istype 'collapse';  " 5 pt.
 	N_PZ_469  node istype 'collapse';  " 5 pt.
 	N_PZ_479  node istype 'collapse';  " 1 pt.
 	N_PZ_550  node istype 'collapse';  " 2 pt.
 	N_PZ_570  node istype 'collapse';  " 1 pt.
 	N_PZ_579  node istype 'collapse';  " 1 pt.
 	N_PZ_594  node istype 'collapse';  " 4 pt.
 	N_PZ_595  node istype 'collapse';  " 4 pt.
 	N_PZ_596  node istype 'collapse';  " 4 pt.
 	N_PZ_597  node istype 'collapse';  " 4 pt.
 	N_PZ_623  node istype 'collapse';  " 1 pt.
 	dvm/N1007  node ;  " 1 pt.
 	dvm/N1011  node ;  " 1 pt.
 	dvm/N1013  node ;  " 1 pt.
 	dvm/N1040  node ;  " 1 pt.
 	dvm/N1044  node ;  " 2 pt.
 	dvm/N1718  node ;  " 2 pt.
 	dvm/N1821  node ;  " 1 pt.
 	dvm/N1868  node ;  " 1 pt.
 	dvm/N1955  node ;  " 1 pt.
 	dvm/N2005  node ;  " 1 pt.
 	dvm/N2064  node ;  " 1 pt.
 	dvm/N2114  node ;  " 1 pt.
 	dvm/N2164  node ;  " 1 pt.
 	dvm/N2210  node ;  " 1 pt.
 	dvm/N374  node ;  " 1 pt.
 	dvm/N377  node ;  " 1 pt.
 	dvm/N461  node ;  " 1 pt.
 	dvm/N5442  node ;  " 7 pt.
 	dvm/N5443  node ;  " 4 pt.
 	dvm/N5444  node ;  " 5 pt.
 	dvm/N5445  node ;  " 6 pt.
 	dvm/N5446  node ;  " 7 pt.
 	dvm/N5447  node ;  " 9 pt.
 	dvm/N5448  node ;  " 10 pt.
 	dvm/N5449  node ;  " 10 pt.
 	dvm/addr_set  node ;  " 4 pt.
 	dvm/dm_num_0  node ;  " 7 pt.
 	dvm/dm_num_1  node ;  " 6 pt.
 	dvm/dm_num_2  node ;  " 4 pt.
 	dvm/dm_sng_ln0_flag  node ;  " 2 pt.
 	dvm/dm_sng_ln1_flag  node ;  " 2 pt.
 	dvm/dm_sng_ln2_flag  node ;  " 2 pt.
 	dvm/dm_sng_ln3_flag  node ;  " 2 pt.
 	dvm/dm_sng_ln4_flag  node ;  " 2 pt.
 	dvm/dm_sng_ln5_flag  node ;  " 2 pt.
 	dvm/dm_sng_ln6_flag  node ;  " 2 pt.
 	dvm/dm_sng_ln7_flag  node ;  " 2 pt.
 	dvm/main_curr_state_FFD1  node ;  " 5 pt.
 	dvm/main_curr_state_FFD2  node ;  " 4 pt.
 	dvm/main_curr_state_FFD3  node ;  " 4 pt.
 	dvm/main_curr_state_FFD4  node ;  " 2 pt.
 	dvm/shift_curr_state_FFT1  node ;  " 6 pt.
 	dvm/shift_curr_state_FFT2  node ;  " 1 pt.
 	dvm/shift_data/N133  node ;  " 2 pt.
 	dvm/wr_addr24_flag  node ;  " 3 pt.
 	dvm/wr_addr3_flag  node ;  " 2 pt.
 	dvm/wr_addr4_flag  node ;  " 2 pt.
 	dvm/wr_addr5_flag  node ;  " 2 pt.
 	dvm/wr_addr6_flag  node ;  " 2 pt.
 	dvm/wr_addr7_flag  node ;  " 2 pt.
 	dvm/wr_reg_num_0  node ;  " 5 pt.
 	dvm/wr_reg_num_1  node ;  " 5 pt.
 	dvm/wr_reg_num_2  node ;  " 4 pt.
 	reset_button  node K4 ;  " 1 pt.
 

xpla property 'USER_SLEW_RATE a<0> a<10> a<11> a<12> a<13> a<14> a<15> a<16> a<17> a<18> a<19> 
	a<1> a<20> a<21> a<22> a<2> a<3> a<4> a<5> a<6> a<7> a<8> a<9> ad_chip2_enn busy_test chip3_en convert 
	d<0> d<10> d<11> d<12> d<13> d<14> d<15> d<1> d<2> d<3> d<4> d<5> d<6> d<7> d<8> d<9> din flash_cs0n 
	flash_wr_protect io13 led1_sel led2_sel led3_sel led4_sel oen osc_cntrl reset_adn reset_memn 
	rise_fall rwn sclk sp_a_0 sp_d<0> sp_d<10> sp_d<11> sp_d<12> sp_d<13> sp_d<14> sp_d<15> sp_d<1> 
	sp_d<2> sp_d<3> sp_d<4> sp_d<5> sp_d<6> sp_d<7> sp_d<8> sp_d<9> sram_cs1n sram_low_byten sram_upper_byten 
	'; 
EQUATIONS 

! N363.AR = reset_button.Q;		"--- [PT=1, FI=1, LVL=1] ---
 N363.CLK = cclk;		"--- [PT=1, FI=1, LVL=1] ---
"**** xor synthesis: shared-pt 6 --> 3
 N363.T.X1 = N363.Q & !N_PZ_469;		"--- [PT=1, FI=2, LVL=5] ---
 N363.T.X2 = N363.Q & !dvm/main_curr_state_FFD4.Q & !