📄 top_level.ann
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"XPLAOPT Version 9.99.99.99
"Device Name: XCR3256XL-7CS280
"Created on: Jan 29 11:17:04 2002
MODULE top_level
"******** 1 Clock/Input Pin(s) *********************************************
cclk PIN D11;
"******** 29 Input Pin(s) **************************************************
busy PIN T14;
dout PIN T10;
sp_a<10> PIN F17;
sp_a<11> PIN H17;
sp_a<12> PIN M18;
sp_a<13> PIN L17;
sp_a<14> PIN E18;
sp_a<15> PIN K18;
sp_a<16> PIN H19;
sp_a<17> PIN L16;
sp_a<18> PIN M17;
sp_a<19> PIN E19;
sp_a<1> PIN T17;
sp_a<20> PIN F19;
sp_a<21> PIN H18;
sp_a<22> PIN J18;
sp_a<23> PIN L18;
sp_a<2> PIN R16;
sp_a<3> PIN R17;
sp_a<4> PIN N16;
sp_a<5> PIN M16;
sp_a<6> PIN R19;
sp_a<7> PIN N18;
sp_a<8> PIN K17;
sp_a<9> PIN J17;
sp_cs0n PIN B19;
sp_cs1n PIN G16;
sp_oen PIN G17;
sp_wen PIN F18;
"******** 78 Output Pin(s) *************************************************
a<0> PIN T5;
a<10> PIN V5;
a<11> PIN W5;
a<12> PIN W4;
a<13> PIN W3;
a<14> PIN U6;
a<15> PIN T6;
a<16> PIN R6;
a<17> PIN W7;
a<18> PIN G1;
a<19> PIN U5;
a<1> PIN W10;
a<20> PIN U4;
a<21> PIN G2;
a<22> PIN G4;
a<2> PIN T9;
a<3> PIN U9;
a<4> PIN T8;
a<5> PIN V7;
a<6> PIN U7;
a<7> PIN T7;
a<8> PIN V6;
a<9> PIN W6;
ad_chip2_enn PIN U10;
busy_test PIN E1;
chip3_en PIN M3;
convert PIN W14;
d<0> PIN A14;
d<10> PIN B12;
d<11> PIN D10;
d<12> PIN C9;
d<13> PIN B8;
d<14> PIN C7;
d<15> PIN B7;
d<1> PIN B13;
d<2> PIN D12;
d<3> PIN A12;
d<4> PIN C10;
d<5> PIN C8;
d<6> PIN D7;
d<7> PIN A7;
d<8> PIN C13;
d<9> PIN A13;
din PIN W11;
flash_cs0n PIN E14;
flash_wr_protect PIN H2;
io13 PIN E2;
led1_sel PIN G3;
led2_sel PIN F4;
led3_sel PIN F3;
led4_sel PIN F5;
oen PIN D14;
osc_cntrl PIN V13;
reset_adn PIN R14;
reset_memn PIN T13;
rise_fall PIN U11;
rwn PIN J2;
sclk PIN W12;
sp_a_0 PIN U19;
sp_d<0> PIN V16;
sp_d<10> PIN U15;
sp_d<11> PIN C16;
sp_d<12> PIN A16;
sp_d<13> PIN B17;
sp_d<14> PIN B18;
sp_d<15> PIN F15;
sp_d<1> PIN W15;
sp_d<2> PIN T15;
sp_d<3> PIN D15;
sp_d<4> PIN E15;
sp_d<5> PIN A15;
sp_d<6> PIN A17;
sp_d<7> PIN A18;
sp_d<8> PIN V15;
sp_d<9> PIN T16;
sram_cs1n PIN K2;
sram_low_byten PIN K3;
sram_upper_byten PIN J3;
"******** 107 Node(s) ******************************************************
N363 NODE 371;
N373 NODE 376;
N383 NODE 374;
N393 NODE 373;
N403 NODE 365;
N413 NODE 403;
N423 NODE 402;
N433 NODE 401;
N443 NODE 400;
N453 NODE 399;
N463 NODE 398;
N473 NODE 370;
N483 NODE 408;
N493 NODE 395;
N503 NODE 419;
N513 NODE 369;
N523 NODE 321;
N533 NODE 320;
N543 NODE 319;
N553 NODE 328;
N563 NODE 368;
N573 NODE 367;
N583 NODE 366;
N634 NODE 339;
N644 NODE 338;
N654 NODE 388;
N664 NODE 381;
N674 NODE 380;
N684 NODE 379;
N694 NODE 337;
N704 NODE 336;
N714 NODE 335;
N724 NODE 334;
N734 NODE 378;
N744 NODE 377;
N754 NODE 435;
N764 NODE 434;
N774 NODE 433;
N813 NODE 449;
N825 NODE 432;
N_PZ_445 NODE 389;
N_PZ_450 NODE 359;
N_PZ_452 NODE 390;
N_PZ_469 NODE 318;
N_PZ_479 NODE 448;
N_PZ_550 NODE 342;
N_PZ_570 NODE 285;
N_PZ_579 NODE 412;
N_PZ_594 NODE 362;
N_PZ_595 NODE 413;
N_PZ_596 NODE 431;
N_PZ_597 NODE 467;
N_PZ_623 NODE 293;
dvm/N1007 NODE 451;
dvm/N1011 NODE 425;
dvm/N1013 NODE 454;
dvm/N1040 NODE 430;
dvm/N1044 NODE 429;
dvm/N1718 NODE 410;
dvm/N1821 NODE 416;
dvm/N1868 NODE 415;
dvm/N1955 NODE 414;
dvm/N2005 NODE 424;
dvm/N2064 NODE 423;
dvm/N2114 NODE 422;
dvm/N2164 NODE 421;
dvm/N2210 NODE 420;
dvm/N374 NODE 426;
dvm/N377 NODE 427;
dvm/N461 NODE 411;
dvm/N5442 NODE 353;
dvm/N5443 NODE 350;
dvm/N5444 NODE 360;
dvm/N5445 NODE 297;
dvm/N5446 NODE 351;
dvm/N5447 NODE 352;
dvm/N5448 NODE 287;
dvm/N5449 NODE 288;
dvm/addr_set NODE 322;
dvm/dm_num_0 NODE 354;
dvm/dm_num_1 NODE 355;
dvm/dm_num_2 NODE 347;
dvm/dm_sng_ln0_flag NODE 387;
dvm/dm_sng_ln1_flag NODE 386;
dvm/dm_sng_ln2_flag NODE 385;
dvm/dm_sng_ln3_flag NODE 418;
dvm/dm_sng_ln4_flag NODE 384;
dvm/dm_sng_ln5_flag NODE 383;
dvm/dm_sng_ln6_flag NODE 382;
dvm/dm_sng_ln7_flag NODE 417;
dvm/main_curr_state_FFD1 NODE 323;
dvm/main_curr_state_FFD2 NODE 289;
dvm/main_curr_state_FFD3 NODE 294;
dvm/main_curr_state_FFD4 NODE 292;
dvm/shift_curr_state_FFT1 NODE 290;
dvm/shift_curr_state_FFT2 NODE 291;
dvm/shift_data/N133 NODE 450;
dvm/wr_addr24_flag NODE 302;
dvm/wr_addr3_flag NODE 307;
dvm/wr_addr4_flag NODE 305;
dvm/wr_addr5_flag NODE 304;
dvm/wr_addr6_flag NODE 303;
dvm/wr_addr7_flag NODE 306;
dvm/wr_reg_num_0 NODE 296;
dvm/wr_reg_num_1 NODE 295;
dvm/wr_reg_num_2 NODE 286;
reset_button NODE 489;
"******** 1 Input Register Node(s) *****************************************
N624 NODE T10;
EQUATIONS
"********( N363 )***********************************************************
"PLA 3 pts
N363.T = (N363.Q & !N_PZ_469
) $ (!dvm/main_curr_state_FFD3.Q
& !dvm/main_curr_state_FFD1.Q & dvm/N1044 & !N363.Q
& !dvm/main_curr_state_FFD4.Q & dvm/main_curr_state_FFD2.Q
# !dvm/main_curr_state_FFD3.Q & !dvm/main_curr_state_FFD1.Q
& N363.Q & !N_PZ_452 & !N_PZ_469
& !dvm/main_curr_state_FFD4.Q & dvm/main_curr_state_FFD2.Q);
!N363.AR = reset_button.Q; "GCT(FB6)
N363.C = cclk;
"********( N373 )***********************************************************
"PLA 3 pts
N373.D = !dvm/main_curr_state_FFD3.Q & !dvm/main_curr_state_FFD1.Q
& dvm/N1044 & !N583.Q & N_PZ_452
& !dvm/main_curr_state_FFD4.Q & N373.Q
& dvm/main_curr_state_FFD2.Q
# !dvm/main_curr_state_FFD3.Q & N523.Q
& !dvm/main_curr_state_FFD1.Q & dvm/N1044 & N513.Q & N543.Q
& N473.Q & N583.Q & N363.Q & N_PZ_452 & N573.Q & N563.Q
& N553.Q & !dvm/main_curr_state_FFD4.Q & !N373.Q & N533.Q
& dvm/main_curr_state_FFD2.Q
# !N_PZ_594 & N373.Q;
!N373.AR = reset_button.Q; "GCT(FB6)
N373.C = cclk;
"********( N383 )***********************************************************
"PLA 2 pts
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