ms32pci.vhd

vhdl 写的 PCI IP核程序

             end if;

             if DEVSEL_N'Last_Event <= tsetup then    
                report "DEVSEL_N  setup time violation"
                   severity Warning;
             end if; 

             --- inset IRDY_N if loop_irdy =1 and nr_irdy >1   
             if loop_irdy =1 then
                while  (nr_irdy > 1) loop
                   IRDY_N <='1' after tdelay;    
                   nr_irdy   := nr_irdy -1 ;
                  wait until FALLING_EDGE(CLK);                       
                end loop;  
                IRDY_N <='0' after tdelay;    
             end if;          
   
             -- terminate cycle because DEVSEL_N is anactive 
             -- (implement command MASTER-ABORT TERMINATION )   
             if start_irdy = 0 then   -- terminate cycle
                stop := true;
                FRAME_N <='1'; -- after tdelay;                                  
             end if;
     
             --   wait until FALLING_EDGE(CLK);                       
             -- repeat until all data are read or  STOP_N ='0'
             while ((data_number > 0) and (stop = false)) loop  -- read cycle  
                parity_flag <= true;
                data_number := data_number -1;
                parity_flag <= true;
                data_read := data(data_nr - data_number);
                if data_number = 0 then
                   C_BE_Bus(3 downto 0) <=bus_sel(data_nr) after tdelay; 
                   data_read := data(data_nr);      
                else 
                   C_BE_Bus(3 downto 0) <=bus_sel(data_nr - data_number+1) after tdelay;
                   data_read := data(data_nr - data_number);
                end if; 

                parity_flag <= true;
                if data_number =0 then
                   FRAME_N <='1';-- after tdelay;                           
                end if;

                -- exit cycle if RST_N or STOP_N are active
                if RESET = 1 or STOP_N = '0' or STOP_N = 'L' then       
                   stop := true;             -- exit cycle 
                   irdy_insert := false;
                end if;

                if irdy_insert = true and (data_nr - data_number) = loop_irdy  then
                   -- insert IRDY ='1' if insert_trdy =true 
                   while nr_irdy > 1 loop
                      nr_irdy   := nr_irdy -1 ;
                      IRDY_N <= '1' after tdelay;    -- insert IRDY
                      -- exit cycle if RST_N or STOP_N are active
                      if RESET = 1 or STOP_N = '0' or STOP_N = 'L' then       
                         stop := true;               -- exit cycle
                         nr_irdy := 1;
                      end if;                    
                     wait until FALLING_EDGE(CLK);
                   end loop; -- end loop nr_irdy
                end if; -- end if irdy_insert                         
                    
                --  IRDY_N <= '0' after tdelay; 
                if data_number = 0 then
                   IRDY_N <= '0' after tdelay;       
                end if;        
               wait until RISING_EDGE(CLK);
    
                if TRDY_N'Last_Event <= tsetup then    -- end of cycle
                   report "TRDY_N setup time violation"
                      severity Warning;
                end if;
       
                -- wait for TRDY_N = '0' (maxim 8 clock pulse)       
                while TRDY_N = '1' and trdy_exit = false loop      
                   wait until RISING_EDGE(CLK);
                   -- wait maxim 8 clock pulse if TRDY is asserted
                    trdy_stop := trdy_stop -1;   
                    if trdy_stop = 0 then
                       stop := true;
                       report "Target is not responding "
                          severity Warning;
                       FRAME_N <= '1';-- after tdelay;  
                       IRDY_N <= '1' after tdelay;
                       trdy_exit := true;
                    end if; 

                    -- exit cycle if RST_N or STOP_N are active
                    if RESET = 1 or STOP_N = '0' or STOP_N = 'L' then      
                       stop := true;                        -- exit cycle
                       trdy_exit := true;
                    end if;                         
                end loop; -- end loop TRDY_N=1                  

                Vec2Hex (data_read,str8,Good2);
                report "        EXPECTED DATA= "&str8 &"";  -- display expected data   

                Vec2Hex (AD_Bus,str8,Good2);
                report "        READ DATA= "&str8 &"";      -- display receive data

                if  AD_Bus'Last_Event <= tsetup then        -- end of cycle
                    report "AD_BUS setup time violation"
                       severity Warning;
                end if;
                   
                if ((data_number >0) and (stop =false)) then
                   wait until FALLING_EDGE(CLK);
                end if;

               wait for thold;
                if AD_Bus'Last_Event <= thold then    -- end of cycle
                   report "AD_Bus hold time violation"
                      severity Warning;
                end if;             
             end loop; -- end loop data_number

             if RESET =1 or STOP_N ='0' or STOP_N ='L' then      
                AD_Bus(31 downto 0) <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ" after tdelay;
                C_BE_Bus(3 downto 0) <= "ZZZZ" after tdelay;  
                FRAME_N <= 'Z';-- after tdelay;                                  
                IRDY_N <= 'Z' after tdelay;
                parity_now <= 'Z' after tdelay;
                REQ_N <= 'H' after tdelay;
                parity_flag <= false;
             end if;                         
           else
           --------------------------------------------------------------------
           -- BEGIN WRITE CYCLE                                              --
           --------------------------------------------------------------------
              -- adress phase 
              parity_flag <= false;
              nr_irdy := nr_irdy;
              AD_Bus(31 downto 0) <= address(31 downto 0) after tdelay; -- set address
              C_BE_Bus(3 downto 0) <= bus_cmd(3 downto 0)after tdelay;  -- set command
              FRAME_N <= '0'; -- after tdelay;
              IRDY_N <= '1' after tdelay;
              parity_read <= 'Z';      
              parity(address(31 downto 0), bus_cmd(3 downto 0), parity_temp); -- calculate  parity of address cycle
              parity_now <= parity_temp after tdelay;
             wait until FALLING_EDGE(CLK);
              -- end adress phase                

              REQ_N <='1';

              parity_flag <= false;
              IRDY_N <= '0' after tdelay;    
              --  wait for 1 ns;
              -- wait for DEVSEL_N = '0' 
              -- (implement command MASTER-ABORT TERMINATION if TARGET not respond)
              while ((start_irdy > 0) and (DEVSEL_N ='H' or DEVSEL_N ='Z' or DEVSEL_N ='X') ) loop           -- wait for the number of IRDY state
                 start_irdy := start_irdy -1;        -- from the begining of read cycle  
                wait until FALLING_EDGE(CLK);
              end loop;

              -- if device not respond then exits the write command
              if start_irdy = 0 then   -- terminate cycle
                 stop := true;
                 FRAME_N <= '1';-- after tdelay;                                  
              end if;

              if DEVSEL_N'Last_Event <= tsetup then    
                 report "DEVSEL_N  setup time violation"
                    severity Warning;
              end if; 

              while ((data_number >0) and (stop =false)) loop
                 -- data phase
                 data_number := data_number -1;       
                 AD_Bus(31 downto 0) <= data(data_nr - data_number) after tdelay;      -- set DATA
                 C_BE_Bus(3 downto 0) <= bus_sel(data_nr - data_number) after tdelay;  -- set BE#s
                 IRDY_N <= '0' after tdelay;
                 parity(data(data_nr - data_number), bus_sel(data_nr - data_number), parity_temp); -- calculate  parity
                 parity_now <= parity_temp after tdelay;
                 -- end data phase
            
                 if data_number = 0 then
                    FRAME_N <= '1';-- after tdelay;
                 end if;    

                 -- exit cycle if RST_N,GNT_N or STOP_N are active
                 if RESET = 1 or STOP_N= '0' or STOP_N = 'L' then       
                    stop := true;                                -- exit cycle
                 end if;

                wait until RISING_EDGE(CLK);

                 if TRDY_N'Last_Event <= tsetup then    -- end of cycle
                    report "TRDY_N setup time violation"
                       severity Warning;
                 end if;

                 -- wait for TRDY_N ='0'       
                 while TRDY_N ='1' and   trdy_exit = false loop
                    wait until RISING_EDGE(CLK); 
                     -- wait maxim 8 clock pulse if TRDY is asserted
                     trdy_stop := trdy_stop -1;
                     if trdy_stop = 0 then
                        stop := true;
                        report "Target is not responding "
                           severity Warning;
                        FRAME_N <= '1';-- after tdelay;  
                        IRDY_N <= '1' after tdelay;
                        trdy_exit := true;                                
                     end if;                       

                     -- exit cycle if RST_N,GNT_N or STOP_N are active
                     if RESET = 1 or STOP_N = '0' or STOP_N = 'L' then       
                        stop := true;                       -- exit cycle
                        trdy_exit := true;
                     end if;
                 end loop; -- end loop TRDY=1            
      
                 if ((data_number > 0)  and (stop = false)) then
                    wait until FALLING_EDGE(CLK); -- synchronize with PCICLK
                 end if;
                 -- insert IRDY_N                               
                 if irdy_insert = true and (data_nr -data_number) = loop_irdy  
                            and data_number >0 and (stop =false) then 
                    while nr_irdy > 1 loop  
                       IRDY_N <='1' after tdelay;                                                                                    
                       nr_irdy := nr_irdy -1 ;   
                       if nr_irdy > 0 then
                          if data_number > 0 then
                             C_BE_Bus(3 downto 0) <=bus_sel(data_nr - data_number +1) after tdelay;  -- set BE#s
                             parity(data(data_nr - data_number), bus_sel(data_nr - data_number+1), parity_temp); -- calculate  parity        
                             parity_now <= parity_temp after tdelay;          
                          end if;
                       wait until FALLING_EDGE(CLK);
                       end if;

                       if RESET = 1 or STOP_N = '0' or STOP_N = 'L' then       
                          stop := true;                               -- exit cycle
                          nr_irdy := 1;
                       end if;                   
                    end loop;  -- end loop nr_irdy                                 
                 end if;         
                 report "        WRITE DATA= "&str8 &"";      -- display write data
            end loop; -- end loop start_irdy > 0 ...

            if RESET = 1 or STOP_N = '0' or STOP_N = 'L' then      
               AD_Bus(31 downto 0) <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ" after tdelay;
               C_BE_Bus(3 downto 0) <= "ZZZZ" after tdelay;  
               FRAME_N <= 'Z';-- after tdelay;                                  
               IRDY_N <= 'Z' after tdelay;
               parity_now <= 'Z' after tdelay;
               REQ_N <= 'H' after tdelay;
               parity_flag <= false;
            end if;                                    
          end if; -- end rd_wr = '1'
       end if; -- if RST_N ='0' then
     end READ_WRITE;
     --------------------------------------------------------------------------
     --  Procedure implement instruction WRSW                                --
     --------------------------------------------------------------------------
     -- Writes single DWORD to memory space!
     procedure WRSW(
        data        : in    Data_buffer;
        address     : inout STD_LOGIC_VECTOR(31 downto 0);
        data_number : in    Integer;
        bus_sel     : in    Data_Enable) is
        variable   bus_cmd  : STD_LOGIC_VECTOR(3 downto 0);
        variable str8,str_8 : string(1 to 8);
        variable Good2      : Boolean;
     begin
        bus_cmd := "0111";
        address(1 downto 0) := "00";
        Vec2Hex (data(1),str8,Good2);
        Vec2Hex (address,str_8,Good2);      
        report "Write single DWORD to memory space! Address : "&str_8;
        READ_WRITE(address,data,1,bus_cmd,bus_sel,'0');
     end WRSW;
     --------------------------------------------------------------------------
     --  Procedure implement instruction RDSW                                --
     --------------------------------------------------------------------------