cic2_by4_compiler_v1_0.vhd

cic抽取滤波器ip核

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-- You must compile the wrapper file cic2_by4_compiler_v1_0.vhd when simulating
-- the core, cic2_by4_compiler_v1_0. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".

-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
Library XilinxCoreLib;
-- synthesis translate_on
ENTITY cic2_by4_compiler_v1_0 IS
	port (
	din: IN std_logic_VECTOR(15 downto 0);
	nd: IN std_logic;
	clk: IN std_logic;
	dout: OUT std_logic_VECTOR(17 downto 0);
	rdy: OUT std_logic;
	rfd: OUT std_logic);
END cic2_by4_compiler_v1_0;

ARCHITECTURE cic2_by4_compiler_v1_0_a OF cic2_by4_compiler_v1_0 IS
-- synthesis translate_off
component wrapped_cic2_by4_compiler_v1_0
	port (
	din: IN std_logic_VECTOR(15 downto 0);
	nd: IN std_logic;
	clk: IN std_logic;
	dout: OUT std_logic_VECTOR(17 downto 0);
	rdy: OUT std_logic;
	rfd: OUT std_logic);
end component;

-- Configuration specification 
	for all : wrapped_cic2_by4_compiler_v1_0 use entity XilinxCoreLib.cic_compiler_v1_0(behavioral)
		generic map(
			c_num_stages => 6,
			c_list_rates => "4,5",
			c_num_channels => 1,
			c_has_rounding => 0,
			c_diff_delay => 1,
			c_input_width => 16,
			c_use_dsp => 1,
			c_filter_type => 1,
			c_sample_freq => 280000000,
			c_overclock => 1,
			c_has_sclr => 0,
			c_rate_type => 0,
			c_min_rate => 4,
			c_has_ce => 0,
			c_family => "virtex4",
			c_clk_freq => 280000000,
			c_rate => 4,
			c_max_rate => 4,
			c_num_rates => 2,
			c_component_name => "cic2_by4_compiler_v1_0",
			c_xdevicefamily => "virtex4",
			c_output_width => 18);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_cic2_by4_compiler_v1_0
		port map (
			din => din,
			nd => nd,
			clk => clk,
			dout => dout,
			rdy => rdy,
			rfd => rfd);
-- synthesis translate_on

END cic2_by4_compiler_v1_0_a;