cic2_by4_compiler_v1_0.xco

cic抽取滤波器ip核

##############################################################
#
# Xilinx Core Generator version J.40
# Date: Tue Nov 18 23:48:16 2008
#
##############################################################
#
#  This file contains the customisation parameters for a
#  Xilinx CORE Generator IP GUI. It is strongly recommended
#  that you do not manually alter this file as it may cause
#  unexpected and unsupported behavior.
#
##############################################################
#
# BEGIN Project Options
SET addpads = False
SET asysymbol = False
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = False
SET designentry = VHDL
SET device = xc4vfx12
SET devicefamily = virtex4
SET flowvendor = Other
SET formalverification = False
SET foundationsym = False
SET implementationfiletype = Ngc
SET package = sf363
SET removerpms = False
SET simulationfiles = Behavioral
SET speedgrade = -10
SET verilogsim = False
SET vhdlsim = True
# END Project Options
# BEGIN Select
SELECT CIC_Compiler family Xilinx,_Inc. 1.0
# END Select
# BEGIN Parameters
CSET ce=false
CSET clock_frequency=280
CSET component_name=cic2_by4_compiler_v1_0
CSET differential_delay=1
CSET filter_type=Decimation
CSET fixed_or_initial_rate=4
CSET input_data_width=16
CSET input_sample_frequency=280
CSET maximum_rate=4
CSET minimum_rate=4
CSET number_of_channels=1
CSET number_of_stages=6
CSET output_data_width=18
CSET passband_max=0.5
CSET passband_min=0.0
CSET quantization=Truncation
CSET sample_rate_changes=Fixed
CSET sclr=false
CSET stopband_max=1.0
CSET stopband_min=0.5
CSET use_xtreme_dsp_slice=true
# END Parameters
GENERATE
# CRC: 780f2af5