csix_typer.v

Common Switch Interface CSIX-L1 Reference Design

		input_bus,
		ready,
		output_sel,
		vpar_sel,
		clk,
		rst,
		current_vpar
		);


//This module takes in 44-bit data format used in 
//this implementation for transmit and convert it 
//to the 32-bit CSIX format.

input clk, rst;
input [43:0] input_bus;
input [1:0] ready;
input [2:0] output_sel;
input [1:0] vpar_sel;


//Input Bus Data Format:
//
// TYPE/BIT POS   43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
// Idle         :| Type(4)   | Payload Length(8)     | Don't cares(32) also called DC                                                      |
// Unicast      :| Type(4)   | Payload Length(8)     | Class(8)              | Destination Address(12)           | Don't Cares(12)         |
// Multicast M. :| Type(4)   | Payload Length(8)     | Class(8)              | Bitmask Header(8)     | Bitmap(16)                          |
// Multicast ID :| Type(4)   | Payload Length(8)     | Class(8)              | Multicast ID (22)                                       | DC|
// Multicast Bin:| Type(4)   | Payload Length(8)     | Class(8)              | Left Destination Address(12)      | R. Destination Addr(12) |
// Broadcast    :| Type(4)   | Payload Length(8)     | Class(8)              | Don't Cares(24)                                             |
// Flow Control :| Type(4)   | Payload Length(8)     | Class(8)              | FCT | C| P| Speed(4)  | Destination Address(12)     | DC(4) |
// Data         :| Don't Cares(12)                   | Data(32)                                                                            |


output [31:0] output_bus;
output [15:0] current_vpar;
//output [31:0] base_and_vpar;

wire [15:0] base_header;
wire [15:0] ext_header1;
wire [15:0] ext_header2;
wire [15:0] vertical_parity;
wire [15:0] prev_vpar;

wire [1:0] output_sel_delay1;
wire [15:0] sub1_ext1;
wire [15:0] sub1_ext2;
wire [15:0] sub1_ext3;
wire [15:0] sub1_ext4;
wire [15:0] sub1_ext5;
wire [15:0] sub1_ext6;
wire [15:0] sub2_ext1;
wire [15:0] sub2_ext2;
wire [15:0] sub2_ext3;
wire [15:0] sub2_ext4;
wire [15:0] sub2_ext5;
wire [15:0] sub2_ext6;
wire [15:0] ext_header2_delay1;
wire [15:0] byte2n3_delay1;

wire [31:0] base_and_vpar;
wire [31:0] base_and_ext1;
wire [31:0] ext2_and_data;
wire [31:0] data_and_data;
wire [31:0] data_and_vpar;


//Base Header Construction
assign base_header = {ready[1:0], input_bus[43:40], 2'b00, input_bus[39:32]}; //Creates Base Header


//Extension Header Byte 2 and 3 Construction
assign sub1_ext1 = {input_bus[31:24], 8'b00000000}; //Creates byte 2 and 3 of Unicast Ext. Header
assign sub1_ext2 = input_bus[31:16]; //Creates byte 2 and 3 of Multicast M. Ext. Header
assign sub1_ext3 = {input_bus[31:24], 2'b00, input_bus[23:18]}; //Creates byte 2 and 3 of Multicast ID Ext. Header
assign sub1_ext4 = input_bus[31:16]; //Creates byte 2 and 3 of Multicast Bin Ext. Header
assign sub1_ext5 = {input_bus[31:24], 8'b00000000}; //Creates byte 2 and 3 of Broadcast Ext. Header
assign sub1_ext6 = input_bus[31:16];

sixteen_bit_mux6_to_1 EXT_HEADER1_MUX(.out(ext_header1), .i1(sub1_ext1), .i2(sub1_ext2), .i3(sub1_ext3), .i4(sub1_ext4), .i5(sub1_ext5), .i6(sub1_ext6), .sel(input_bus[42:40]));

assign base_and_ext1 = {base_header,ext_header1};


//Extension Header Byte 4 and 5 Construction
assign sub2_ext1 = {4'b0000, input_bus[23:12]}; //Creates byte 4 and 5 of Unicast Ext. Header
assign sub2_ext2 = input_bus[15:0]; //Creates byte 4 and 5 of Multicast M. Ext. Header
assign sub2_ext3 = input_bus[17:2]; //Creates byte 4 and 5 of Multicast ID Header
assign sub2_ext4 = input_bus[15:0]; //Creates byte 4 and 5 of Multicast Bin Ext. Header
assign sub2_ext5 = 16'b0000000000000000; //Creates byte 4 and 5 of Broadcast Ext. Header
assign sub2_ext6 = {4'b0000, input_bus[15:4]};

sixteen_bit_mux6_to_1 EXT_HEADER2_MUX(.out(ext_header2), .i1(sub2_ext1), .i2(sub2_ext2), .i3(sub2_ext3), .i4(sub2_ext4), .i5(sub2_ext5), .i6(sub2_ext6), .sel(input_bus[42:40]));
sixteen_bit_reg DELAYING_EXT_HEADER2(.q(ext_header2_delay1), .clk(clk), .rst(rst), .d(ext_header2));

assign ext2_and_data = {ext_header2_delay1,input_bus[31:16]};


//Registers for Data Synchronization at CSIX, and Data_and_Data Construction
sixteen_bit_reg DELAYING_BYTE2N3_OF_DATA(.q(byte2n3_delay1), .clk(clk), .rst(rst), .d(input_bus[15:0]));

assign data_and_data = {byte2n3_delay1,input_bus[31:16]};


//Vertical Parity for Idle Inst. Construction
assign base_and_vpar = {base_header[15:14],4'b0000,base_header[9:0],~base_header[15:14],4'b1111,~base_header[9:0]};

//Select the output and additional pipelining
wire [31:0] base_and_vpar1, base_and_ext11, ext2_and_data1, data_and_data1, data_and_vpar1;
wire [2:0] output_sel1;

thirtytwo_bit_reg BAV(.q(base_and_vpar1), .clk(clk), .rst(rst), .d(base_and_vpar));
thirtytwo_bit_reg BAE(.q(base_and_ext11), .clk(clk), .rst(rst), .d(base_and_ext1));
thirtytwo_bit_reg EAD(.q(ext2_and_data1), .clk(clk), .rst(rst), .d(ext2_and_data));
thirtytwo_bit_reg DAD(.q(data_and_data1), .clk(clk), .rst(rst), .d(data_and_data));
thirtytwo_bit_reg DAV(.q(data_and_vpar1), .clk(clk), .rst(rst), .d(data_and_vpar));
one_bit_reg OS0(.q(output_sel1[0]), .clk(clk), .rst(rst), .d(output_sel[0]));
one_bit_reg OS1(.q(output_sel1[1]), .clk(clk), .rst(rst), .d(output_sel[1]));
one_bit_reg OS2(.q(output_sel1[2]), .clk(clk), .rst(rst), .d(output_sel[2]));
thirtytwo_bit_mux5_to_1 SELECTS_OUTPUT(.out(output_bus), .i0(base_and_vpar1), .i1(base_and_ext11), .i2(ext2_and_data1), .i3(data_and_data1), .i4(data_and_vpar1), .sel(output_sel1));


//Data and Vertical Parity Construction
vertical_parity_generator VERTICAL_PARITY_UNIT(.clk(clk), .rst(rst), .sel(vpar_sel), .first16bit(output_bus[31:16]), .second16bit(output_bus[15:0]), .current_vpar(current_vpar), .prev_vpar(prev_vpar));
assign data_and_vpar = {byte2n3_delay1,16'h0000};

endmodule


module thirtytwo_bit_mux2_to_1(out, i0, i1, sel);

input [31:0] i0, i1;
input sel;

output [31:0] out;
reg [31:0] out;

always@(i0 or i1 or sel)
 case(sel)
  1'b0: out = i0;
  1'b1: out = i1;
  default: out = i0;
 endcase

endmodule


module thirtytwo_bit_mux5_to_1(out, i0, i1, i2, i3, i4, sel);

input [31:0] i0, i1, i2, i3, i4;
input [2:0] sel;

output [31:0] out;
reg [31:0] out;

always@(i0 or i1 or i2 or i3 or i4 or sel)
 case(sel)
  3'b000: out = i0;
  3'b001: out = i1;
  3'b010: out = i2;
  3'b011: out = i3;
  3'b100: out = i4;
  default: out = i0;
 endcase
 
endmodule


module sixteen_bit_mux6_to_1(out, i1, i2, i3, i4, i5, i6, sel);

//This mux is designed for and unique to this CSIX implementation

input [15:0] i1, i2, i3, i4, i5, i6;
input [2:0] sel;

output [15:0] out;
reg [15:0] out;

always@(i1 or i2 or i3 or i4 or i5 or i6 or sel)
 case(sel)
  3'b001: out = i1;
  3'b010: out = i2;
  3'b011: out = i3;
  3'b100: out = i4;
  3'b101: out = i5;
  3'b110: out = i6;
  default: out = i1;
 endcase

endmodule


module four_bit_reg(q, clk, rst, d);

input clk, rst;
input [3:0] d;

output [3:0] q;

one_bit_reg BIT0(.q(q[0]), .clk(clk), .rst(rst), .d(d[0]));
one_bit_reg BIT1(.q(q[1]), .clk(clk), .rst(rst), .d(d[1]));
one_bit_reg BIT2(.q(q[2]), .clk(clk), .rst(rst), .d(d[2]));
one_bit_reg BIT3(.q(q[3]), .clk(clk), .rst(rst), .d(d[3]));

endmodule


module fortyfour_bit_reg(q, clk, rst, d);

input clk, rst;
input [43:0] d;

output [43:0] q;


one_bit_reg BIT0(.q(q[0]), .clk(clk), .rst(rst), .d(d[0]));
one_bit_reg BIT1(.q(q[1]), .clk(clk), .rst(rst), .d(d[1]));
one_bit_reg BIT2(.q(q[2]), .clk(clk), .rst(rst), .d(d[2]));
one_bit_reg BIT3(.q(q[3]), .clk(clk), .rst(rst), .d(d[3]));
one_bit_reg BIT4(.q(q[4]), .clk(clk), .rst(rst), .d(d[4]));
one_bit_reg BIT5(.q(q[5]), .clk(clk), .rst(rst), .d(d[5]));
one_bit_reg BIT6(.q(q[6]), .clk(clk), .rst(rst), .d(d[6]));
one_bit_reg BIT7(.q(q[7]), .clk(clk), .rst(rst), .d(d[7]));
one_bit_reg BIT8(.q(q[8]), .clk(clk), .rst(rst), .d(d[8]));
one_bit_reg BIT9(.q(q[9]), .clk(clk), .rst(rst), .d(d[9]));
one_bit_reg BIT10(.q(q[10]), .clk(clk), .rst(rst), .d(d[10]));
one_bit_reg BIT11(.q(q[11]), .clk(clk), .rst(rst), .d(d[11]));
thirtytwo_bit_reg BIT0TO31(.q(q[43:12]), .clk(clk), .rst(rst), .d(d[43:12]));

endmodule


module fortyeight_bit_reg(q, clk, rst, d);

input clk, rst;
input [47:0] d;

output [47:0] q;

thirtytwo_bit_reg BIT0TO31(.q(q[31:0]), .clk(clk), .rst(rst), .d(d[31:0]));
sixteen_bit_reg BIT32TO47(.q(q[47:32]), .clk(clk), .rst(rst), .d(d[47:32]));

endmodule


module thirtytwo_bit_reg(q, clk, rst, d);

input clk, rst;
input [31:0] d;

output [31:0] q;

sixteen_bit_reg BIT0TO15(.q(q[15:0]), .clk(clk), .rst(rst), .d(d[15:0]));
sixteen_bit_reg BIT16TO31(.q(q[31:16]), .clk(clk), .rst(rst), .d(d[31:16]));


endmodule


module sixteen_bit_reg(q, clk, rst, d);

input clk, rst;
input [15:0] d;

output [15:0] q;

one_bit_reg BIT0(.q(q[0]), .clk(clk), .rst(rst), .d(d[0]))/*synthesis syn_noprune = 1*/;
one_bit_reg BTI1(.q(q[1]), .clk(clk), .rst(rst), .d(d[1]))/*synthesis syn_noprune = 1*/;
one_bit_reg BIT2(.q(q[2]), .clk(clk), .rst(rst), .d(d[2]))/*synthesis syn_noprune = 1*/;
one_bit_reg BIT3(.q(q[3]), .clk(clk), .rst(rst), .d(d[3]))/*synthesis syn_noprune = 1*/;
one_bit_reg BIT4(.q(q[4]), .clk(clk), .rst(rst), .d(d[4]))/*synthesis syn_noprune = 1*/;
one_bit_reg BIT5(.q(q[5]), .clk(clk), .rst(rst), .d(d[5]))/*synthesis syn_noprune = 1*/;
one_bit_reg BIT6(.q(q[6]), .clk(clk), .rst(rst), .d(d[6]))/*synthesis syn_noprune = 1*/;
one_bit_reg BIT7(.q(q[7]), .clk(clk), .rst(rst), .d(d[7]))/*synthesis syn_noprune = 1*/;
one_bit_reg BIT8(.q(q[8]), .clk(clk), .rst(rst), .d(d[8]))/*synthesis syn_noprune = 1*/;
one_bit_reg BIT9(.q(q[9]), .clk(clk), .rst(rst), .d(d[9]))/*synthesis syn_noprune = 1*/;
one_bit_reg BIT10(.q(q[10]), .clk(clk), .rst(rst), .d(d[10]))/*synthesis syn_noprune = 1*/;
one_bit_reg BIT11(.q(q[11]), .clk(clk), .rst(rst), .d(d[11]))/*synthesis syn_noprune = 1*/;
one_bit_reg BIT12(.q(q[12]), .clk(clk), .rst(rst), .d(d[12]))/*synthesis syn_noprune = 1*/;
one_bit_reg BIT13(.q(q[13]), .clk(clk), .rst(rst), .d(d[13]))/*synthesis syn_noprune = 1*/;
one_bit_reg BIT14(.q(q[14]), .clk(clk), .rst(rst), .d(d[14]))/*synthesis syn_noprune = 1*/;
one_bit_reg BIT15(.q(q[15]), .clk(clk), .rst(rst), .d(d[15]))/*synthesis syn_noprune = 1*/;

endmodule


module one_bit_reg(q, clk, rst, d);

input clk, rst, d;

output q;

reg q/*synthesis syn_noprune = 1*/;

always@(posedge clk or negedge rst)
begin
 if(rst == 1'b0)
  q = 1'b0;
 else
  q = d;
end

endmodule


module count_to_256(clk, rst, count, counter_value);

//This module counts from 0 to 511, and used in
//CSIX to keep track the number of bytes being
//received or transmitted.

input clk, rst, count;
output [8:0] counter_value;

reg [8:0] counter_value_preserver/*synthesis syn_noprune = 1*/;

assign counter_value = (count) ? counter_value_preserver + 4 : 9'b000000000;

always@(posedge clk or negedge rst)
 if(rst == 1'b0)
   counter_value_preserver = 9'b000000000;
 else
   counter_value_preserver = counter_value;

endmodule


module horizontal_parity_generator_32bit(data, TxPar);

//This module calculates the horizontal parity used in CSIX

input [31:0] data;
output TxPar;

assign TxPar = ^data;

endmodule


module vertical_parity_generator(clk, rst, sel, first16bit, second16bit, current_vpar, prev_vpar);

//This module calculates the vertical parity used in CSIX

input clk, rst;
input [1:0] sel;
input [15:0] first16bit, second16bit;
output [15:0] current_vpar, prev_vpar;

reg [15:0] current_vpar;

wire [15:0] prev_vpar;

sixteen_bit_reg SIXTEEN_BIT_REG_FOR_PREV_VPAR(.q(prev_vpar), .clk(clk), .rst(rst), .d(current_vpar));

always@(first16bit or second16bit or sel or prev_vpar)
 begin
  case(sel)
   2'b00: current_vpar = 16'h0000;
   2'b01: current_vpar = first16bit ^ second16bit;
   2'b10: current_vpar = prev_vpar ^ first16bit ^ second16bit;
   2'b11: current_vpar = prev_vpar ^ first16bit;
   default: current_vpar = 16'h0000;
  endcase  
 end

endmodule


module fortyfour_bit_mux8_to_1(out, i0, i1, i2, i3, i4, i5, i6, i7, sel);

input [43:0] i0, i1, i2, i3, i4, i5, i6, i7;
input [2:0] sel;

output [43:0] out;
reg [43:0] out;

always@(i0 or i1 or i2 or i3 or i4 or i5 or i6 or i7 or sel)
 case(sel)
  3'b000: out = i0;
  3'b001: out = i1;
  3'b010: out = i2;
  3'b011: out = i3;
  3'b100: out = i4;
  3'b101: out = i5;
  3'b110: out = i6;
  3'b111: out = i7;
  default: out = i0;
 endcase
 
endmodule