csix_typer.v

Common Switch Interface CSIX-L1 Reference Design

	input_bus,
	output_sel_inv,
	clk,
	rst	
	);

//This module takes in CSIX format 32-bit data received and
//convert it to the 44-bit format used in this implementation.

input clk, rst;
input [31:0] input_bus;
input [2:0] output_sel_inv;

output [43:0] output_bus;

wire [31:0] byte1n2;
wire [43:0] idle_type;
wire [43:0] unicast_type;
wire [43:0] multicastm_type;
wire [43:0] multicastid_type;
wire [43:0] multicastbin_type;
wire [43:0] broadcast_type;
wire [43:0] flowcontrol_type;
wire [43:0] data_type;

//Output Bus Data Format:
//
// TYPE/BIT POS   43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
// Idle         :| Type(4)   | Payload Length(8)     | Don't cares(32) also called DC                                                      |
// Unicast      :| Type(4)   | Payload Length(8)     | Class(8)              | Destination Address(12)           | Don't Cares(12)         |
// Multicast M. :| Type(4)   | Payload Length(8)     | Class(8)              | Bitmask Header(8)     | Bitmap(16)                          |
// Multicast ID :| Type(4)   | Payload Length(8)     | Class(8)              | Multicast ID (22)                                       | DC|
// Multicast Bin:| Type(4)   | Payload Length(8)     | Class(8)              | Left Destination Address(12)      | R. Destination Addr(12) |
// Broadcast    :| Type(4)   | Payload Length(8)     | Class(8)              | Don't Cares(24)                                             |
// Flow Control :| Type(4)   | Payload Length(8)     | Class(8)              | FCT | C| P| Speed(4)  | Destination Address(12)     | DC(4) |
// Data         :| Don't Cares(12)                   | Data(32)                                                                            |

thirtytwo_bit_reg DELAYING_BYTE1N2(.q(byte1n2), .clk(clk), .rst(rst), .d(input_bus));

//Building the appropriate 44-bit data format from the input.
assign idle_type = {byte1n2[29:26], byte1n2[23:16], 32'h00000000};
assign unicast_type = {byte1n2[29:26], byte1n2[23:16], byte1n2[15:8], input_bus[27:16], 12'h000};
assign multicastm_type = {byte1n2[29:26], byte1n2[23:16], byte1n2[15:0], input_bus[31:16]};
assign multicastid_type = {byte1n2[29:26], byte1n2[23:16], byte1n2[15:8], byte1n2[5:0], input_bus[31:16], 2'b00};
assign multicastbin_type = {byte1n2[29:26], byte1n2[23:0], input_bus[31:16]};
assign broadcast_type = {byte1n2[29:26], byte1n2[23:16], byte1n2[15:8], 24'h000000};
assign flowcontrol_type = {byte1n2[29:26], byte1n2[23:16], byte1n2[15:0], input_bus[27:16], 4'h0};
assign data_type = {12'h000, byte1n2[15:0], input_bus[31:16]};

fortyfour_bit_mux8_to_1 OUTPUT_BUS_MUX(.out(output_bus), .i0(idle_type), .i1(unicast_type), .i2(multicastm_type), .i3(multicastid_type), .i4(multicastbin_type), .i5(broadcast_type), .i6(flowcontrol_type), .i7(data_type), .sel(output_sel_inv));

endmodule


module csix_inv_state_machine(
	RxSOF,
	RxData_type,
	RxData_info,
	RxData_type1,
	counter_value_inv,
	clk,
	rst,
	output_sel_inv,
	count_inv,
	end_of_transmission,
	vpar_sel_inv
	);

//This state machine controls the data flow and signals
//during receiving of data.

input clk, rst;
input RxSOF;
input [3:0] RxData_type;
input [8:0] RxData_info;
input [3:0] RxData_type1;
input [8:0] counter_value_inv;


output [2:0] output_sel_inv;
output count_inv;
output end_of_transmission;
output [1:0] vpar_sel_inv;


reg [2:0] current_state;
reg [2:0] next_state;
reg count_inv;
reg [8:0] payload_num_received_preserver;
reg [2:0] output_sel_inv;
reg end_of_transmission;
reg [1:0] vpar_sel_inv;

wire [8:0] payload_num_received;

assign payload_num_received = (RxSOF == 1'b1) ? RxData_info : payload_num_received_preserver;

always@(posedge clk or negedge rst)
begin
 if(rst == 1'b0)
  begin
   current_state = 3'b001;
   payload_num_received_preserver = 9'b000000000;
  end
 else
  begin
   current_state = next_state;
   payload_num_received_preserver = payload_num_received;
  end
end

always@(current_state or RxSOF or RxData_type or RxData_type1 or RxData_info or counter_value_inv or payload_num_received)
 begin
  //States are in terms of the action at the 1st stage.
  output_sel_inv = 3'b000;
  end_of_transmission = 1'b0;
  case(current_state)
   3'b001: begin       
    if((RxSOF != 1'b0) && (RxData_type != 4'b0000))
     begin
      output_sel_inv = RxData_type[2:0];
      count_inv = 1'b0;
      vpar_sel_inv = 2'b01;
      next_state = 3'b010;
     end
    else
     begin
      count_inv = 1'b0;
      vpar_sel_inv = 2'b00;
      next_state = 3'b001;
     end
   end
   3'b010: begin
    output_sel_inv = RxData_type1[2:0];
    count_inv = 1'b1;
    vpar_sel_inv = 2'b10;
    if(counter_value_inv >= (payload_num_received + 4))
     vpar_sel_inv = 2'b11;
    if(counter_value_inv >= (payload_num_received + 8))
     begin
      end_of_transmission = 1'b1;
      vpar_sel_inv = 2'b11;
      next_state = 3'b001;
     end
    else
     next_state = 3'b100;
   end
   3'b100: begin
    count_inv = 1'b1;
    output_sel_inv = 3'b111;
    vpar_sel_inv = 2'b10;
    if(counter_value_inv >= (payload_num_received + 4))
     vpar_sel_inv = 2'b11;
    if(counter_value_inv >= (payload_num_received + 8))
     begin
      vpar_sel_inv = 2'b11;
      end_of_transmission = 1'b1;      
      next_state = 3'b001;
     end
    else
     next_state = 3'b100;
    if(RxSOF != 1'b0)
     begin
      vpar_sel_inv = 2'b01;
      end_of_transmission = 1'b1;      
      count_inv = 1'b0;
      next_state = 3'b010;
     end
   end
   default: begin
    output_sel_inv = 3'b000;
    count_inv = 1'b0;
    end_of_transmission = 1'b0;
    vpar_sel_inv = 2'b00;
    next_state = 3'b001;    
   end
  endcase
 end

endmodule


module csix_state_machine(
		clk,
		rst,
		RxData,
		NFR,
		counter_value,
		TxData_info,
		TxSOF,
		ready,
		output_sel,
		get_inst,
		count,
		vpar_sel
		);

//This state machine controls the data flow and signals
//during transmitting of data.

input clk, rst;
input [31:0] RxData;
input [8:0] TxData_info;
input NFR;
input [8:0] counter_value;


output TxSOF;
output [1:0] ready;
output [2:0] output_sel;
output get_inst;
output count;
output [1:0] vpar_sel;


reg [9:0] current_state;
reg [9:0] next_state;
reg TxSOF;
reg [1:0] ready;
reg [2:0] output_sel;
reg get_inst;
reg count;
reg [1:0] vpar_sel;
wire [8:0] payload_num;
reg [8:0] payload_num_preserver;

assign payload_num = (current_state[6] == 1'b1) ? TxData_info : payload_num_preserver;

always@(posedge clk or negedge rst)
begin
 if(rst == 1'b0)
  begin
   current_state = 10'b0000000001;
   payload_num_preserver = 9'b000000000;
  end
 else
  begin
   current_state = next_state;
   payload_num_preserver = payload_num;
  end
end

always@(current_state or RxData or NFR or counter_value or TxData_info or payload_num)
 begin
  //States are in terms of the action at the output. Control are done in previous step.  
  TxSOF = 1'b0;  
  get_inst = 1'b0;
  count = 1'b0;
  vpar_sel = 2'b00;
  case(current_state)
   10'b0000000001: begin
    //Reset State
    ready = 2'b00;
    output_sel = 3'b000;
    next_state = 10'b0000000010;
   end
   10'b0000000010: begin
    //Transmit Idle w. ready bit = 0 after reset state
    ready = 2'b00;
    output_sel = 3'b000;
    next_state = 10'b0000000100;
   end
   10'b0000000100: begin
    //Receiving Idle w. ready bit = 0 state
    output_sel = 3'b000;
    if(RxData[29:26] == 4'b0000)
     begin      
      ready = 2'b11;
      next_state = 10'b0000001000;
     end
    else
     begin
      ready = 2'b00;
      next_state = 10'b0000000100;
     end
   end
   10'b0000001000: begin
    //Receiving Idle w. ready bit = 1 state
    output_sel = 3'b000;
    if(RxData[31:30] == 2'b11)
     begin
      ready = 2'b11;
      get_inst = 1'b1;
      next_state = 10'b0000010000;
     end
    else
     begin
      ready = 2'b00;
      next_state = 10'b0000001000;
     end
   end
   10'b0000010000: begin
    //Beginning of Normal Operations steps
    //Send Dead Cycle State
    ready = 2'b11;
    if(NFR == 1'b0)
     begin
      output_sel = 3'b000;
      next_state = 10'b0000100000;
     end
    else
     begin
      output_sel = 3'b001;
      vpar_sel = 2'b10;
      next_state = 10'b0001000000;
     end
   end
   10'b0000100000: begin
    //Send Idle CFrame State
    output_sel = 3'b000;
    ready = 2'b11;
    TxSOF = 1'b1;
    get_inst = 1'b1;
    next_state = 10'b0000010000;
   end
   10'b0001000000: begin
    //Send Start of Frame State (Base and Ext. 1)
    ready = 2'b11;
    TxSOF = 1'b1;
    vpar_sel = 2'b10;
    output_sel = 3'b010; 
    //payload_num = TxData_info;
    next_state = 10'b0010000000;
   end
   10'b0010000000: begin
    //Send Start of Frame State (Ext. 2 and 2 Bytes of Data)
    vpar_sel = 2'b10;
    count = 1'b1;
    if(counter_value >= payload_num)
     begin
      ready = 2'b11;
      output_sel = 3'b100;
      get_inst = 1'b1;
      vpar_sel = 2'b11;
      next_state = 10'b1000000000;  
     end
    else
     begin
      ready = 2'b11;
      output_sel = 3'b011;
      next_state = 10'b0100000000;
     end
   end
   10'b0100000000: begin
    //Send Normal Frame State (4 bytes of Data)    
    count = 1'b1;
    if(counter_value >= payload_num)
     begin
      ready = 2'b11;
      output_sel = 3'b100;
      get_inst = 1'b1;
      vpar_sel = 2'b11;
      next_state = 10'b1000000000;
     end
    else
     begin
      ready = 2'b11;
      output_sel = 3'b011;
      vpar_sel = 2'b10;
      next_state = 10'b0100000000;
     end
   end   
   10'b1000000000: begin   
    //Send final data and Vertical Parity
    ready = 2'b11;
    if(NFR == 1'b1)
     begin     
      output_sel = 3'b001;
      vpar_sel = 2'b01;
      next_state = 10'b0001000000;
     end
    else
     begin
      output_sel = 3'b000;
      next_state = 10'b0000010000;      
     end
   end
   default: begin
    vpar_sel = 2'b00;
    next_state = 10'b0000000001;
    ready = 2'b00;
    output_sel = 3'b000;
    count = 1'b0;
   end
  endcase
 end

endmodule


module csix_data_constructor(
		output_bus,