csix_typer.v

Common Switch Interface CSIX-L1 Reference Design

module csix(
	clk,
	rst,
	input_bus,
	output_to_system,
	inst_signal,
	RxData,
	RxPar,
	RxSOF,
	RxClk,
	TxData,
	TxPar,
	TxSOF,
	TxClk,
	get_inst,
	start_of_received,
	end_of_transmission,
	h_par,
	all_data_ok
	);

//This module is all of the CSIX components combined 
//together to form the whole thing. This module
//includes both the Transmit and Receive module.
//This design is a pipeline design of the CSIX
//interface. Pipelining is used in order to achieve
//high clock cycle.

input clk, rst;
input [43:0] input_bus;
input inst_signal;
input [31:0] RxData;
input RxPar, RxSOF, RxClk;

output [31:0] TxData;
output TxPar, TxSOF, TxClk;
output get_inst;
output [43:0] output_to_system;
output start_of_received;
output end_of_transmission;
output h_par;
output all_data_ok;


wire [2:0] output_sel, output_sel_inv; 
wire [1:0] current_state, current_state_inv;
wire [1:0] vpar_sel, vpar_sel_inv;
wire [1:0] ready;
wire [31:0] output_bus;
wire [47:0] input_bus1;
wire [8:0] counter_value;
wire [8:0] counter_value_inv, payload_num_received;
wire count, count_inv;
wire TxPar_before_out, TxPar_before_out1;
wire TxSOF_before_out, TxSOF_before_out1;
wire vpar_sel_at_out;
wire [15:0] current_vpar, prev_vpar;
wire [31:0] TxData_before_out, TxData_before_out1;	
wire [31:0] RxData_at1;
wire RxSOF_at1, RxSOF_at2, RxPar_at1; //RxClk_at1;
wire [43:0] output_bus_at1;
wire [3:0] RxData_type1;
wire eot_at1;
wire RxPar_check;
wire h_par_at1, h_par_at2;
wire [15:0] prev_vpar_inv, vpar_portion;
wire all_data_ok1;
wire [31:0] base_and_vpar;
wire [1:0] vpar_sel1;
wire [43:0] input_bus2;
wire [31:0] RxData_at2;
wire RxSOF_at3, RxPar_at2, RxPar_at3, eot_at2, RxSOF_at4;
wire [8:0] temp_info, temp_info2;		
wire [2:0] output_sel_inv1;
wire [1:0] vpar_sel_inv1;
wire [31:0] RxData_at3;

//Tx Section
assign TxClk = clk; //Transferring clock to other side, also all Rx has RxClk as clock

fortyeight_bit_reg FORTY_BIT_IN_REG(
			.q(input_bus1), 
			.clk(clk), 
			.rst(rst), 
			.d({3'b000,inst_signal,input_bus})); //Bit 47,46,45 can be used for additional controls

fortyfour_bit_reg INFO_ON_TXDATA(.q(input_bus2), .clk(clk), .rst(rst), .d(input_bus1[43:0]));

csix_state_machine CSIX_STATE_MACHINE_UNIT(
			.clk(clk),
			.rst(rst),
			.RxData(RxData_at1),
			.NFR(input_bus1[44]),
			.counter_value(counter_value),
			.TxData_info({(|input_bus2[43:40] & ~(|(input_bus2[39:32]))),input_bus2[39:32]}), //Determines # of bytes being transmitted (LOGIC_BLOCK in Diagram)
			.TxSOF(TxSOF_before_out),
			.ready(ready),
			.output_sel(output_sel),
			.get_inst(get_inst),
			.count(count),
			.vpar_sel(vpar_sel1)
			);

one_bit_reg VS0(.q(vpar_sel[0]), .clk(clk), .rst(rst), .d(vpar_sel1[0]));
one_bit_reg VS1(.q(vpar_sel[1]), .clk(clk), .rst(rst), .d(vpar_sel1[1]));
			
			
count_to_256 DATA_COUNTER(
		.clk(clk), 
		.rst(rst), 
		.count(count), 
		.counter_value(counter_value)
		);

csix_data_constructor CSIX_DATA_CONSTRUCTOR_UNIT(
			.output_bus(output_bus),
			.input_bus(input_bus1[43:0]),
			.ready(ready),
			.output_sel(output_sel),
			.vpar_sel(vpar_sel),
			.clk(clk),
			.rst(rst),
			.current_vpar(current_vpar)
			);

horizontal_parity_generator_32bit HORIZONTAL_PARITY_GEN(
					.data(TxData_before_out1), 
					.TxPar(TxPar_before_out)
					);

thirtytwo_bit_reg OUTPUT_BUS_REG(
			.q(TxData_before_out), 
			.clk(clk),
			.rst(rst), 
			.d(output_bus)
			);

one_bit_reg VPAR_SEL_REG_AT_OUT(
		.q(vpar_sel_at_out), 
		.clk(clk), 
		.rst(rst), 
		.d(&vpar_sel));
		
sixteen_bit_reg PREV_VPAR_REG(
			.q(prev_vpar), 
			.clk(clk), 
			.rst(rst), 
			.d(~current_vpar));

thirtytwo_bit_mux2_to_1 TXDATA_OUTPUT_MUX(
				.out(TxData_before_out1), 
				.i0(TxData_before_out), 
				.i1({TxData_before_out[31:16],prev_vpar}), 
				.sel(vpar_sel_at_out));

one_bit_reg TXPAR_OUT_REG(
		.q(TxPar),
		.rst(rst),
		.clk(clk),
		.d(~TxPar_before_out)
		);
		
		
one_bit_reg TXSOF_OUT_REG(
		.q(TxSOF_before_out1),
		.rst(rst),
		.clk(clk),
		.d(TxSOF_before_out)
		);
		
one_bit_reg TXSOF_OUT_REG1(
		.q(TxSOF),
		.rst(rst),
		.clk(clk),
		.d(TxSOF_before_out1)
		);
		
thirtytwo_bit_reg TXDATA_OUT_REG(
			.q(TxData), 
			.clk(clk),
			.rst(rst), 
			.d(TxData_before_out1)
			);


//Rx Section
thirtytwo_bit_reg RXDATA_IN_REG(
			.q(RxData_at1), 
			.clk(RxClk),
			.rst(rst), 
			.d(RxData)
			);

assign temp_info = {(|RxData_at1[29:26] & ~(|(RxData_at1[23:16]))),RxData_at1[23:16]}; //Determines # bytes to receive (Logic Block in Diagram)

one_bit_reg TEMP_INFO_REG0(.q(temp_info2[0]),.rst(rst),.clk(RxClk),.d(temp_info[0]));
one_bit_reg TEMP_INFO_REG1(.q(temp_info2[1]),.rst(rst),.clk(RxClk),.d(temp_info[1]));
one_bit_reg TEMP_INFO_REG2(.q(temp_info2[2]),.rst(rst),.clk(RxClk),.d(temp_info[2]));
one_bit_reg TEMP_INFO_REG3(.q(temp_info2[3]),.rst(rst),.clk(RxClk),.d(temp_info[3]));
one_bit_reg TEMP_INFO_REG4(.q(temp_info2[4]),.rst(rst),.clk(RxClk),.d(temp_info[4]));
one_bit_reg TEMP_INFO_REG5(.q(temp_info2[5]),.rst(rst),.clk(RxClk),.d(temp_info[5]));
one_bit_reg TEMP_INFO_REG6(.q(temp_info2[6]),.rst(rst),.clk(RxClk),.d(temp_info[6]));
one_bit_reg TEMP_INFO_REG7(.q(temp_info2[7]),.rst(rst),.clk(RxClk),.d(temp_info[7]));
one_bit_reg TEMP_INFO_REG8(.q(temp_info2[8]),.rst(rst),.clk(RxClk),.d(temp_info[8]));

thirtytwo_bit_reg RXDATA_IN_REG1(
			.q(RxData_at2), 
			.clk(RxClk),
			.rst(rst), 
			.d(RxData_at1)
			);
			
one_bit_reg RXSOF_IN_REG(
		.q(RxSOF_at1),
		.rst(rst),
		.clk(RxClk),
		.d(RxSOF)
		);
		
one_bit_reg RXSOF_IN_REG2(
		.q(RxSOF_at2),
		.rst(rst),
		.clk(RxClk),
		.d(RxSOF_at1)
		);

one_bit_reg RXSOF_IN_REG3(
		.q(RxSOF_at3),
		.rst(rst),
		.clk(RxClk),
		.d(RxSOF_at2)
		);
		
one_bit_reg RXSOF_IN_REG4(
		.q(RxSOF_at4),
		.rst(rst),
		.clk(RxClk),
		.d(RxSOF_at3)
		);		
		
one_bit_reg START_OF_RECEIVED_REG(
		.q(start_of_received),
		.rst(rst),
		.clk(RxClk),
		.d(RxSOF_at4)
		);				
		
one_bit_reg RXPAR_IN_REG(
		.q(RxPar_at1),
		.rst(rst),
		.clk(RxClk),
		.d(RxPar)
		);
		
one_bit_reg RXPAR_IN_REG1(
		.q(RxPar_at2),
		.rst(rst),
		.clk(RxClk),
		.d(RxPar_at1)
		);		
		
one_bit_reg RXPAR_IN_REG2(
		.q(RxPar_at3),
		.rst(rst),
		.clk(RxClk),
		.d(RxPar_at2)
		);				
		
count_to_256 DATA_RECEIVED_COUNTER(
		.clk(RxClk), 
		.rst(rst), 
		.count(count_inv), 
		.counter_value(counter_value_inv)
		);

csix_inv_state_machine CSIX_INV_STATE_MACHINE_UNIT(
			.RxSOF(RxSOF_at2),
			.RxData_type(RxData_at2[29:26]),
			.RxData_info(temp_info2),
			.RxData_type1(RxData_type1),
			.counter_value_inv(counter_value_inv),
			.output_sel_inv(output_sel_inv),
			.count_inv(count_inv),
			.clk(RxClk),
			.rst(rst),
			.end_of_transmission(eot_at1),
			.vpar_sel_inv(vpar_sel_inv)
			);
						
one_bit_reg EOT_OUT_REG(
		.q(eot_at2),
		.rst(rst),
		.clk(RxClk),
		.d(eot_at1)
		);
		
one_bit_reg EOT_OUT_REG1(
		.q(end_of_transmission),
		.rst(rst),
		.clk(RxClk),
		.d(eot_at2)
		);		
			
			
four_bit_reg RXDATA_TYPE_REG(
		.q(RxData_type1), 
		.clk(RxClk), 
		.rst(rst), 
		.d(RxData_at2[29:26])
		);


one_bit_reg OSI0(.q(output_sel_inv1[0]), .clk(RxClk), .rst(rst), .d(output_sel_inv[0]));
one_bit_reg OSI1(.q(output_sel_inv1[1]), .clk(RxClk), .rst(rst), .d(output_sel_inv[1]));
one_bit_reg OSI2(.q(output_sel_inv1[2]), .clk(RxClk), .rst(rst), .d(output_sel_inv[2]));

one_bit_reg VSI0(.q(vpar_sel_inv1[0]), .clk(RxClk), .rst(rst), .d(vpar_sel_inv[0]));
one_bit_reg VSI1(.q(vpar_sel_inv1[1]), .clk(RxClk), .rst(rst), .d(vpar_sel_inv[1]));

thirtytwo_bit_reg RXDATA_REG3(.q(RxData_at3), .clk(RxClk), .rst(rst), .d(RxData_at2));
			
csix_data_deconstructor CSIX_DATA_DECONSTRUCTOR_UNIT(
				.output_bus(output_bus_at1),
				.input_bus(RxData_at3),
				.output_sel_inv(output_sel_inv1),
				.clk(RxClk),
				.rst(rst)
				);
							
horizontal_parity_generator_32bit HORIZONTAL_PARITY_CHECK(
					.data(RxData_at3),
					.TxPar(RxPar_check)
					);
									
vertical_parity_generator VERTICAL_PARITY_FOR_RECEIVE(
				.clk(RxClk), 
				.rst(rst), 
				.sel(vpar_sel_inv1),
				.first16bit(RxData_at3[31:16]),
				.second16bit(RxData_at3[15:0]), 
				.current_vpar(), 
				.prev_vpar(prev_vpar_inv)
				);
				
sixteen_bit_reg PREV_VPAR_INV_REG(
			.q(vpar_portion), 
			.clk(RxClk), 
			.rst(rst), 
			.d(RxData_at3[15:0])
			);
			
assign	all_data_ok1 = ~(|((~vpar_portion) ^ prev_vpar_inv)); //Checks the vertical parity (Logic Block 2)
			
one_bit_reg ALL_DATA_OK_REG(
		.q(all_data_ok),
		.rst(rst),
		.clk(RxClk),
		.d(all_data_ok1)
		);				
				

assign h_par_at1 = (RxPar_at3 == ~RxPar_check) ? 1:0; //Checks the horizontal parity (Logic Block 3)

one_bit_reg H_PAR_AT2_REG(
		.q(h_par_at2),
		.rst(rst),
		.clk(RxClk),
		.d(h_par_at1)
		);
		
one_bit_reg H_PAR_REG(
		.q(h_par),
		.rst(rst),
		.clk(RxClk),
		.d(h_par_at2)
		);						
				
fortyfour_bit_reg OUTPUT_BUS_OUT_REG(
			.q(output_to_system), 
			.clk(RxClk),
			.rst(rst), 
			.d(output_bus_at1)
			);
			
					
								
endmodule


module csix_data_deconstructor(
	output_bus,