csix.vhd

Common Switch Interface CSIX-L1 Reference Design

 end process;

 COMB: process(current_state, RxSOF, RxData_type, RxData_type1, RxData_info, counter_value_inv, payload_num_received)
 begin
  --States are in terms of the action at the 1st stage.
  output_sel_inv_sig <= "000";
  end_of_transmission_sig <= '0';
  case current_state is
   when "00" =>
    if((RxSOF /= '0') and (RxData_type /= "0000")) then
      output_sel_inv_sig <= RxData_type(2 downto 0);
      count_inv_sig <= '0';
      vpar_sel_inv_sig <= "01";
      next_state <= "01";
    else
      count_inv_sig <= '0';
      vpar_sel_inv_sig <= "00";
      next_state <= "00";
    end if;
   when "01" =>
    output_sel_inv_sig <= RxData_type1(2 downto 0);
    count_inv_sig <= '1';
    vpar_sel_inv_sig <= "10";
    if(STD_LOGIC_VECTOR(counter_value_inv) >= STD_LOGIC_VECTOR(payload_num_received + "000000100")) then
     vpar_sel_inv_sig <= "11";
    end if;
    if(STD_LOGIC_VECTOR(counter_value_inv) >= STD_LOGIC_VECTOR(payload_num_received + "000001000")) then
     end_of_transmission_sig <= '1';
     vpar_sel_inv_sig <= "11";
     next_state <= "00";
    else
     next_state <= "10";
    end if;
   when "10" =>
    count_inv_sig <= '1';
    output_sel_inv_sig <= "111";
    vpar_sel_inv_sig <= "10";
    if(STD_LOGIC_VECTOR(counter_value_inv) >= STD_LOGIC_VECTOR(payload_num_received + "000000100")) then
     vpar_sel_inv_sig <= "11";
    end if;
    if(STD_LOGIC_VECTOR(counter_value_inv) >= STD_LOGIC_VECTOR(payload_num_received + "000001000")) then
     vpar_sel_inv_sig <= "11";
     end_of_transmission_sig <= '1';      
     next_state <= "00";
    else
     next_state <= "10";
    end if;
    if(RxSOF /= '0') then
     vpar_sel_inv_sig <= "01";
     end_of_transmission_sig <= '1';
     count_inv_sig <= '0';
     next_state <= "01";
    end if;
   when others =>
    output_sel_inv_sig <= "000";
    count_inv_sig <= '0';
    end_of_transmission_sig <= '0';
    vpar_sel_inv_sig <= "00";
    next_state <= "00";    
  end case;
 end process COMB;
 
 count_inv <= count_inv_sig;
 end_of_transmission <= end_of_transmission_sig;
 vpar_sel_inv <= vpar_sel_inv_sig;
 output_sel_inv <= output_sel_inv_sig;
end csix_inv_state_machine_behavior;

------------------------
-- CSIX State Machine --
------------------------


--This state machine controls the data flow and signals
--during transmitting of data.

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity csix_state_machine is
 port(clk, rst, NFR: in std_logic;
      RxData: in std_logic_vector(31 downto 0);
      TxData_info, counter_value: in std_logic_vector(8 downto 0);
      TxSOF, get_inst, count: out std_logic;
      vpar_sel, ready: out std_logic_vector(1 downto 0);
      output_sel: out std_logic_vector(2 downto 0));
end csix_state_machine;
		
architecture csix_state_machine_behavior of csix_state_machine is
signal TxSOF_sig, get_inst_sig, count_sig: std_logic;
signal vpar_sel_sig, ready_sig: std_logic_vector(1 downto 0);
signal output_sel_sig: std_logic_vector(2 downto 0);		
signal current_state, next_state: std_logic_vector(3 downto 0);
signal payload_num, payload_num_preserver: unsigned(8 downto 0);

begin

 SEQ: process(rst, clk)
 begin
  if (rst = '0') then
   current_state <= "0000";
   payload_num_preserver <= "000000000";
  elsif (clk = '1' and clk'event) then
   current_state <= next_state;
   payload_num_preserver <= payload_num;
  end if;
 end process;
 
 PAYLOAD_NUM_LOGIC: process(current_state, TxData_info, payload_num_preserver)
 begin 
  if (current_state = "0110") then
   payload_num <= UNSIGNED(TxData_info);
  else
   payload_num <= payload_num_preserver;
  end if;
 end process;

 COMB: process(current_state, RxData, NFR, counter_value, TxData_info, payload_num)
  begin
  --States are in terms of the action at the output. Control are done in previous step.  
  TxSOF_sig <= '0';  
  get_inst_sig <= '0';
  count_sig <= '0';
  vpar_sel_sig <= "00";
  case current_state is
   when "0000" =>
    --Reset State
    ready_sig <= "00";
    output_sel_sig <= "000";
    next_state <= "0001";
   when "0001" => 
    --Transmit Idle w. ready bit = 0 after reset state
    ready_sig <= "00";
    output_sel_sig <= "000";
    next_state <= "0010";
   when "0010" =>
    --Receiving Idle w. ready bit = 0 state
    output_sel_sig <= "000";
    if (RxData(29 downto 26) = "0000") then
     ready_sig <= "11";
     next_state <= "0011";
    else     
     ready_sig <= "00";
     next_state <= "0010";
    end if;
   when "0011" =>
    --Receiving Idle w. ready bit = 1 state
    output_sel_sig <= "000";
    if (RxData(31 downto 30) = "11") then
     ready_sig <= "11";
     get_inst_sig <= '1';
     next_state <= "0100";
    else
     ready_sig <= "00";
     next_state <= "0011";
    end if;
   when "0100" =>
    --Beginning of Normal Operations steps
    --Send Dead Cycle State
    ready_sig <= "11";
    if (NFR = '0') then
     output_sel_sig <= "000";
     next_state <= "0101";
    else
     output_sel_sig <= "001";
     vpar_sel_sig <= "10";
     next_state <= "0110";
    end if;
   when "0101" =>
    --Send Idle CFrame State
    output_sel_sig <= "000";
    ready_sig <= "11";
    TxSOF_sig <= '1';
    get_inst_sig <= '1';
    next_state <= "0100";
   when "0110" =>
    --Send Start of Frame State (Base and Ext. 1)
    ready_sig <= "11";
    TxSOF_sig <= '1';
    vpar_sel_sig <= "10";
    output_sel_sig <= "010"; 
    next_state <= "0111";
   when "0111" =>
    --Send Start of Frame State (Ext. 2 and 2 Bytes of Data)
    vpar_sel_sig <= "10";
    count_sig <= '1';
    if (STD_LOGIC_VECTOR(counter_value) >= STD_LOGIC_VECTOR(payload_num)) then
     ready_sig <= "11";
     output_sel_sig <= "100";
     get_inst_sig <= '1';
     vpar_sel_sig <= "11";
     next_state <= "1001";     
    else
     ready_sig <= "11";
     output_sel_sig <= "011";
     next_state <= "1000";
    end if;
   when "1000" =>
    --Send Normal Frame State (4 bytes of Data)    
    count_sig <= '1';
    if (STD_LOGIC_VECTOR(counter_value) >= STD_LOGIC_VECTOR(payload_num)) then
     ready_sig <= "11";
     output_sel_sig <= "100";
     get_inst_sig <= '1';
     vpar_sel_sig <= "11";
     next_state <= "1001";
    else     
     ready_sig <= "11";
     output_sel_sig <= "011";
     vpar_sel_sig <= "10";
     next_state <= "1000";
    end if;
   when "1001" =>
    --Send final data and Vertical Parity
    ready_sig <= "11";
    if (NFR = '1') then   
     output_sel_sig <= "001";
     vpar_sel_sig <= "01";
     next_state <= "0110";
    else
     output_sel_sig <= "000";
     next_state <= "0100";
    end if;
   when others => 
    vpar_sel_sig <= "00";    
    ready_sig <= "00";
    output_sel_sig <= "000";
    count_sig <= '0';
    next_state <= "0000";
  end case;
 end process;

 TxSOF <= TxSOF_sig;
 get_inst <= get_inst_sig;
 count <= count_sig;
 vpar_sel <= vpar_sel_sig;
 ready <= ready_sig;
 output_sel <= output_sel_sig;
end csix_state_machine_behavior;

---------------------------
-- CSIX Data Constructor --
---------------------------


--This module takes in 44-bit data format used in 
--this implementation for transmit and convert it 
--to the 32-bit CSIX format.

--Input Bus Data Format:
--
-- TYPE/BIT POS   43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
-- Idle         :| Type(4)   | Payload Length(8)     | Don't cares(32) also called DC                                                      |
-- Unicast      :| Type(4)   | Payload Length(8)     | Class(8)              | Destination Address(12)           | Don't Cares(12)         |
-- Multicast M. :| Type(4)   | Payload Length(8)     | Class(8)              | Bitmask Header(8)     | Bitmap(16)                          |
-- Multicast ID :| Type(4)   | Payload Length(8)     | Class(8)              | Multicast ID (22)                                       | DC|
-- Multicast Bin:| Type(4)   | Payload Length(8)     | Class(8)              | Left Destination Address(12)      | R. Destination Addr(12) |
-- Broadcast    :| Type(4)   | Payload Length(8)     | Class(8)              | Don't Cares(24)                                             |
-- Flow Control :| Type(4)   | Payload Length(8)     | Class(8)              | FCT | C| P| Speed(4)  | Destination Address(12)     | DC(4) |
-- Data         :| Don't Cares(12)                   | Data(32)                                                                            |

library ieee;
use ieee.std_logic_1164.all;
entity csix_data_constructor is
 port(clk, rst: in std_logic;
      output_bus: out std_logic_vector(31 downto 0);
      current_vpar: out std_logic_vector(15 downto 0);
      input_bus: in std_logic_vector(43 downto 0);
      ready, vpar_sel: in std_logic_vector(1 downto 0);
      output_sel: in std_logic_vector(2 downto 0));
end csix_data_constructor;

architecture csix_data_constructor_behavior of csix_data_constructor is
component sixteen_bit_mux6_to_1
 port(sel: in std_logic_vector(2 downto 0);
      i1, i2, i3, i4, i5, i6: in std_logic_vector(15 downto 0);
      out_port: out std_logic_vector(15 downto 0));
end component;
component sixteen_bit_reg
 port(rst, clk: in std_logic;
      d:in std_logic_vector(15 downto 0); 
      q: out std_logic_vector(15 downto 0));
end component;
component thirtytwo_bit_reg
 port(rst, clk: in std_logic;
      d:in std_logic_vector(31 downto 0); 
      q: out std_logic_vector(31 downto 0));
end component;
component one_bit_reg
 port(rst, clk, d:in std_logic; 
      q: out std_logic);
end component;
component thirtytwo_bit_mux5_to_1
 port(sel: in std_logic_vector(2 downto 0);
      i0, i1, i2, i3, i4: in std_logic_vector(31 downto 0);
      out_port: out std_logic_vector(31 downto 0));
end component;
component vertical_parity_generator
 port(clk, rst: in std_logic;
      sel: in std_logic_vector(1 downto 0);
      first16bit, second16bit:in std_logic_vector(15 downto 0); 
      current_vpar, prev_vpar: out std_logic_vector(15 downto 0));
end component;

signal output_sel_delay1: std_logic_vector(1 downto 0);
signal base_header, ext_header1, ext_header2, vertical_parity, prev_vpar, sub1_ext1, sub1_ext2, sub1_ext3,
       sub1_ext4, sub1_ext5, sub1_ext6, sub2_ext1, sub2_ext2, sub2_ext3, sub2_ext4, sub2_ext5, sub2_ext6,
       ext_header2_delay1, byte2n3_delay1, current_vpar_sig: std_logic_vector(15 downto 0);
signal base_and_vpar, base_and_ext1, ext2_and_data, data_and_data, data_and_vpar, output_bus_sig: std_logic_vector(31 downto 0);

--Select the output and additional pipelining
signal base_and_vpar1, base_and_ext11, ext2_and_data1, data_and_data1, data_and_vpar1: std_logic_vector(31 downto 0);
signal output_sel1: std_logic_vector(2 downto 0);

begin
 --Base Header Construction
 base_header <= (ready(1 downto 0) & input_bus(43 downto 40) & "00" & input_bus(39 downto 32)); --Creates Base Header

 --Extension Header Byte 2 and 3 Construction
 sub1_ext1 <= (input_bus(31 downto 24) & "00000000"); --Creates byte 2 and 3 of Unicast Ext. Header
 sub1_ext2 <= input_bus(31 downto 16); --Creates byte 2 and 3 of Multicast M. Ext. Header
 sub1_ext3 <= (input_bus(31 downto 24) & "00" & input_bus(23 downto 18)); --Creates byte 2 and 3 of Multicast ID Ext. Header
 sub1_ext4 <= input_bus(31 downto 16); --Creates byte 2 and 3 of Multicast Bin Ext. Header
 sub1_ext5 <= (input_bus(31 downto 24) & "00000000"); --Creates byte 2 and 3 of Broadcast Ext. Header
 sub1_ext6 <= input_bus(31 downto 16);

 EXT_HEADER1_MUX: sixteen_bit_mux6_to_1 port map(out_port => ext_header1, i1 => sub1_ext1, i2 => sub1_ext2, i3 => sub1_ext3, i4 => sub1_ext4, i5 => sub1_ext5, i6 => sub1_ext6, sel => input_bus(42 downto 40));

 base_and_ext1 <= (base_header & ext_header1);

 --Extension Header Byte 4 and 5 Construction
 sub2_ext1 <= ("0000" & input_bus(23 downto 12)); --Creates byte 4 and 5 of Unicast Ext. Header
 sub2_ext2 <= input_bus(15 downto 0); --Creates byte 4 and 5 of Multicast M. Ext. Header
 sub2_ext3 <= input_bus(17 downto 2); --Creates byte 4 and 5 of Multicast ID Header
 sub2_ext4 <= input_bus(15 downto 0); --Creates byte 4 and 5 of Multicast Bin Ext. Header
 sub2_ext5 <= "0000000000000000"; --Creates byte 4 and 5 of Broadcast Ext. Header
 sub2_ext6 <= ("0000" & input_bus(15 downto 4));

 EXT_HEADER2_MUX: sixteen_bit_mux6_to_1 port map(out_port => ext_header2, i1 => sub2_ext1, i2 => sub2_ext2, i3 => sub2_ext3, i4 => sub2_ext4, i5 => sub2_ext5, i6 => sub2_ext6, sel => input_bus(42 downto 40));
 DELAYING_EXT_HEADER2: sixteen_bit_reg port map(q => ext_header2_delay1, clk => clk, rst => rst, d => ext_header2);

 ext2_and_data <= (ext_header2_delay1 & input_bus(31 downto 16));

 --Registers for Data Synchronization at CSIX, and Data_and_Data Construction
 DELAYING_BYTE2N3_OF_DATA: sixteen_bit_reg port map(q => byte2n3_delay1, clk => clk, rst => rst, d => input_bus(15 downto 0));

 data_and_data <= (byte2n3_delay1 & input_bus(31 downto 16));

 --Vertical Parity for Idle Inst. Construction
 base_and_vpar <= (base_header(15 downto 14) & "0000" & base_header(9 downto 0) & (not(base_header(15 downto 14))) & "1111" & (not(base_header(9 downto 0))));

 BAV: thirtytwo_bit_reg port map(q => base_and_vpar1, clk => clk, rst => rst, d => base_and_vpar);
 BAE: thirtytwo_bit_reg port map(q => base_and_ext11, clk => clk, rst => rst, d => base_and_ext1);
 EAD: thirtytwo_bit_reg port map(q => ext2_and_data1, clk => clk, rst => rst, d => ext2_and_data);
 DAD: thirtytwo_bit_reg port map(q => data_and_data1, clk => clk, rst => rst, d => data_and_data);
 DAV: thirtytwo_bit_reg port map(q => data_and_vpar1, clk => clk, rst => rst, d => data_and_vpar);
 OS0: one_bit_reg port map(q => output_sel1(0), clk => clk, rst => rst, d => output_sel(0));
 OS1: one_bit_reg port map(q => output_sel1(1), clk => clk, rst => rst, d => output_sel(1));
 OS2: one_bit_reg port map(q => output_sel1(2), clk => clk, rst => rst, d => output_sel(2));
 SELECTS_OUTPUT: thirtytwo_bit_mux5_to_1 port map(out_port => output_bus_sig, i0 => base_and_vpar1, i1 => base_and_ext11, i2 => ext2_and_data1, i3 => data_and_data1, i4 => data_and_vpar1, sel => output_sel1);

 --Data and Vertical Parity Construction
 VERTICAL_PARITY_UNIT: vertical_parity_generator port map(clk => clk, rst => rst, sel => vpar_sel, first16bit => output_bus_sig(31 downto 16), second16bit => output_bus_sig(15 downto 0), current_vpar => current_vpar_sig, prev_vpar => prev_vpar);
 data_and_vpar <= (byte2n3_delay1 & "0000000000000000");

 output_bus <= output_bus_sig;
 current_vpar <= current_vpar_sig;
end csix_data_constructor_behavior;

----------------------------
-- Thirty-Two Bit 2:1 Mux --
----------------------------


library ieee;
use ieee.std_logic_1164.all;
entity thirtytwo_bit_mux2_to_1 is
 port(sel: in std_logic;
      i0, i1: in std_logic_vector(31 downto 0);
      out_port: out std_logic_vector(31 downto 0));
end thirtytwo_bit_mux2_to_1;

architecture thirtytwo_bit_mux2_to_1_behavior of thirtytwo_bit_mux2_to_1 is
begin