csix.vhd

Common Switch Interface CSIX-L1 Reference Design

---------------------
-- CSIX Top Module --
---------------------


--This module is all of the CSIX components combined 
--together to form the whole thing. This module
--includes both the Transmit and Receive module.
--This design is a pipeline design of the CSIX
--interface. Pipelining is used in order to achieve
--high clock cycle.

library ieee;
use ieee.std_logic_1164.all;
entity csix is
 port(clk, rst, RxPar, RxSOF, RxClk, inst_signal: in std_logic;
      RxData: in std_logic_vector(31 downto 0);
      input_bus:in std_logic_vector(43 downto 0);
      TxPar, TxSOF, TxClk, get_inst, start_of_received, end_of_transmission, h_par, all_data_ok: out std_logic;
      TxData: out std_logic_vector(31 downto 0);
      output_to_system: out std_logic_vector(43 downto 0));
end csix;

architecture csix_behavior of csix is
component fortyeight_bit_reg
 port(rst, clk: in std_logic;
      d:in std_logic_vector(47 downto 0); 
      q: out std_logic_vector(47 downto 0));
end component;
component fortyfour_bit_reg
 port(rst, clk: in std_logic;
      d:in std_logic_vector(43 downto 0); 
      q: out std_logic_vector(43 downto 0));
end component;
component csix_state_machine
 port(clk, rst, NFR: in std_logic;
      RxData: in std_logic_vector(31 downto 0);
      TxData_info, counter_value: in std_logic_vector(8 downto 0);
      TxSOF, get_inst, count: out std_logic;
      vpar_sel, ready: out std_logic_vector(1 downto 0);
      output_sel: out std_logic_vector(2 downto 0));
end component;
component one_bit_reg
 port(rst, clk, d:in std_logic; 
      q: out std_logic);
end component;
component count_to_256
 port(clk, rst, count: in std_logic;
      counter_value: out std_logic_vector(8 downto 0));
end component;
component csix_data_constructor
 port(clk, rst: in std_logic;
      output_bus: out std_logic_vector(31 downto 0);
      current_vpar: out std_logic_vector(15 downto 0);
      input_bus: in std_logic_vector(43 downto 0);
      ready, vpar_sel: in std_logic_vector(1 downto 0);
      output_sel: in std_logic_vector(2 downto 0));
end component;
component horizontal_parity_generator_32bit
 port(data:in std_logic_vector(31 downto 0); 
      TxPar: out std_logic);
end component;
component thirtytwo_bit_reg
 port(rst, clk: in std_logic;
      d:in std_logic_vector(31 downto 0); 
      q: out std_logic_vector(31 downto 0));
end component;
component sixteen_bit_reg
 port(rst, clk: in std_logic;
      d:in std_logic_vector(15 downto 0); 
      q: out std_logic_vector(15 downto 0));
end component;
component thirtytwo_bit_mux2_to_1
 port(sel: in std_logic;
      i0, i1: in std_logic_vector(31 downto 0);
      out_port: out std_logic_vector(31 downto 0));
end component;
component csix_inv_state_machine
 port(clk, rst, RxSOF: in std_logic;
      RxData_type, RxData_type1: in std_logic_vector(3 downto 0);
      RxData_info, counter_value_inv: in std_logic_vector(8 downto 0);
      count_inv, end_of_transmission: out std_logic;
      vpar_sel_inv: out std_logic_vector(1 downto 0);
      output_sel_inv: out std_logic_vector(2 downto 0));
end component;
component four_bit_reg
 port(rst, clk:in std_logic; 
      d:in std_logic_vector(3 downto 0); 
      q: out std_logic_vector(3 downto 0));
end component;
component csix_data_deconstructor
 port(clk, rst: in std_logic;
      output_bus: out std_logic_vector(43 downto 0);
      input_bus: in std_logic_vector(31 downto 0);
      output_sel_inv: in std_logic_vector(2 downto 0));
end component;
component vertical_parity_generator
 port(clk, rst: in std_logic;
      sel: in std_logic_vector(1 downto 0);
      first16bit, second16bit:in std_logic_vector(15 downto 0); 
      current_vpar, prev_vpar: out std_logic_vector(15 downto 0));
end component;

signal count, count_inv, TxPar_before_out, TxPar_before_out1, TxSOF_before_out, TxSOF_before_out1, vpar_sel_at_out, RxSOF_at1,
       RxSOF_at2, RxPar_at1, eot_at1, RxPar_check, h_par_at1, h_par_at2, all_data_ok1, RxSOF_at3, RxPar_at2, RxPar_at3, eot_at2,
       RxSOF_at4, temp1, temp2, temp3, temp1inv, temp2inv, temp3inv, bitwise_or_then_not, vpar_sel_and, not_TxPar_before_out: std_logic;
signal current_state, current_state_inv, vpar_sel, vpar_sel_inv, ready, vpar_sel1, vpar_sel_inv1: std_logic_vector(1 downto 0);
signal output_sel, output_sel_inv, output_sel_inv1: std_logic_vector(2 downto 0);
signal RxData_type1: std_logic_vector(3 downto 0);
signal counter_value, counter_value_inv, payload_num_received, temp_info, temp_info2, TxData_info_in: std_logic_vector(8 downto 0);
signal current_vpar, prev_vpar, prev_vpar_inv, vpar_portion, not_vpar_portion, after_xor, not_current_vpar: std_logic_vector(15 downto 0);
signal output_bus, TxData_before_out, TxData_before_out1, RxData_at1, base_and_vpar, RxData_at2, RxData_at3,
       TxData_before_out_and_prev_vpar: std_logic_vector(31 downto 0);
signal output_bus_at1, input_bus2: std_logic_vector(43 downto 0);
signal input_bus1, unified_input_bus: std_logic_vector(47 downto 0);
  
begin

 --Tx Section
 TxClk <= clk; --Transferring clock to other side, also all Rx has RxClk as clock
 
 unified_input_bus <= ("000" & inst_signal & input_bus);
 FORTY_BIT_IN_REG: fortyeight_bit_reg port map(q => input_bus1, clk => clk, rst => rst, d => unified_input_bus); --Bit 47,46,45 can be used for additional controls
 
 INFO_ON_TXDATA: fortyfour_bit_reg port map(q => input_bus2, clk => clk, rst => rst, d => input_bus1(43 downto 0));
 
 --Determines # of bytes being transmitted (LOGIC_BLOCK in Diagram)
 temp1 <= (input_bus2(43) or input_bus2(42) or input_bus2(41) or input_bus2(40));
 temp2 <= not (input_bus2(39) or input_bus2(38) or input_bus2(37) or input_bus2(36) or input_bus2(35) or input_bus2(34) or input_bus2(33) or input_bus2(32));
 temp3 <= temp1 and temp2;
 TxData_info_in <= (temp3 & input_bus2(39 downto 32));
 
 CSIX_STATE_MACHINE_UNIT: csix_state_machine port map(clk => clk, rst => rst, RxData => RxData_at1, NFR=> input_bus1(44), counter_value => counter_value,
                            TxData_info => TxData_info_in, TxSOF => TxSOF_before_out, ready => ready, output_sel => output_sel, get_inst => get_inst,
                            count => count, vpar_sel => vpar_sel1);

 VS0: one_bit_reg port map(q => vpar_sel(0), clk => clk, rst => rst, d => vpar_sel1(0));
 VS1: one_bit_reg port map(q => vpar_sel(1), clk => clk, rst => rst, d => vpar_sel1(1));

 DATA_COUNTER: count_to_256 port map(clk => clk, rst => rst, count => count, counter_value => counter_value);

 CSIX_DATA_CONSTRUCTOR_UNIT: csix_data_constructor port map(output_bus => output_bus, input_bus => input_bus1(43 downto 0), ready => ready, output_sel => output_sel,
                               vpar_sel => vpar_sel, clk => clk, rst => rst, current_vpar => current_vpar);

 HORIZONTAL_PARITY_GEN: horizontal_parity_generator_32bit port map(data => TxData_before_out1, TxPar => TxPar_before_out);

 OUTPUT_BUS_REG: thirtytwo_bit_reg port map(q => TxData_before_out, clk => clk, rst => rst, d => output_bus);

 vpar_sel_and <= (vpar_sel(1) and vpar_sel(0));
 VPAR_SEL_REG_AT_OUT: one_bit_reg port map( q => vpar_sel_at_out, clk => clk, rst => rst, d => vpar_sel_and);

 not_current_vpar <= not(current_vpar);
 PREV_VPAR_REG: sixteen_bit_reg port map(q => prev_vpar, clk => clk, rst => rst, d => not_current_vpar);

 TxData_before_out_and_prev_vpar <= (TxData_before_out(31 downto 16) & prev_vpar);
 TXDATA_OUTPUT_MUX: thirtytwo_bit_mux2_to_1 port map(out_port => TxData_before_out1, i0 => TxData_before_out, i1 => TxData_before_out_and_prev_vpar, sel => vpar_sel_at_out); 

 not_TxPar_before_out <= not(TxPar_before_out);
 TXPAR_OUT_REG: one_bit_reg port map(q => TxPar, rst => rst, clk => clk, d => not_TxPar_before_out);

 TXSOF_OUT_REG: one_bit_reg port map(q => TxSOF_before_out1, rst => rst, clk => clk, d => TxSOF_before_out);

 TXSOF_OUT_REG1: one_bit_reg port map(q => TxSOF, rst => rst, clk => clk, d => TxSOF_before_out1);

 TXDATA_OUT_REG: thirtytwo_bit_reg port map(q => TxData, clk => clk, rst => rst, d => TxData_before_out1);


 --Rx Section
 RXDATA_IN_REG: thirtytwo_bit_reg port map(q => RxData_at1, clk => RxClk, rst => rst, d => RxData); 

 temp1inv <= (RxData_at1(29) or RxData_at1(28) or RxData_at1(27) or RxData_at1(26));
 temp2inv <= not (RxData_at1(23) or RxData_at1(22) or RxData_at1(21) or RxData_at1(20) or RxData_at1(19) or RxData_at1(18) or RxData_at1(17) or RxData_at1(16));
 temp3inv <= temp1inv and temp2inv;
 temp_info <= (temp3inv & RxData_at1(23 downto 16)); 

 TEMP_INFO_REG0: one_bit_reg port map(q => temp_info2(0), rst => rst, clk => RxClk, d => temp_info(0));
 TEMP_INFO_REG1: one_bit_reg port map(q => temp_info2(1), rst => rst, clk => RxClk, d => temp_info(1));
 TEMP_INFO_REG2: one_bit_reg port map(q => temp_info2(2), rst => rst, clk => RxClk, d => temp_info(2));
 TEMP_INFO_REG3: one_bit_reg port map(q => temp_info2(3), rst => rst, clk => RxClk, d => temp_info(3));
 TEMP_INFO_REG4: one_bit_reg port map(q => temp_info2(4), rst => rst, clk => RxClk, d => temp_info(4));
 TEMP_INFO_REG5: one_bit_reg port map(q => temp_info2(5), rst => rst, clk => RxClk, d => temp_info(5));
 TEMP_INFO_REG6: one_bit_reg port map(q => temp_info2(6), rst => rst, clk => RxClk, d => temp_info(6));
 TEMP_INFO_REG7: one_bit_reg port map(q => temp_info2(7), rst => rst, clk => RxClk, d => temp_info(7));
 TEMP_INFO_REG8: one_bit_reg port map(q => temp_info2(8), rst => rst, clk => RxClk, d => temp_info(8)); 

 RXDATA_IN_REG1: thirtytwo_bit_reg port map(q => RxData_at2, clk => RxClk, rst => rst, d => RxData_at1);

 RXSOF_IN_REG: one_bit_reg port map(q => RxSOF_at1, rst => rst, clk => RxClk, d => RxSOF);

 RXSOF_IN_REG2: one_bit_reg port map(q => RxSOF_at2, rst => rst, clk => RxClk, d => RxSOF_at1);

 RXSOF_IN_REG3: one_bit_reg port map(q => RxSOF_at3, rst => rst, clk => RxClk, d => RxSOF_at2);

 RXSOF_IN_REG4: one_bit_reg port map(q => RxSOF_at4, rst => rst, clk => RxClk, d => RxSOF_at3);
 
 START_OF_RECEIVED_REG: one_bit_reg port map(q => start_of_received, rst => rst, clk => RxClk, d => RxSOF_at4);				
		
 RXPAR_IN_REG: one_bit_reg port map(q => RxPar_at1, rst => rst, clk => RxClk, d => RxPar);
		
 RXPAR_IN_REG1: one_bit_reg port map(q => RxPar_at2, rst => rst, clk => RxClk, d => RxPar_at1);
		
 RXPAR_IN_REG2: one_bit_reg port map(q => RxPar_at3, rst => rst, clk => RxClk, d => RxPar_at2);

 DATA_RECEIVED_COUNTER: count_to_256 port map(clk => RxClk, rst => rst, count => count_inv, counter_value => counter_value_inv);

 CSIX_INV_STATE_MACHINE_UNIT: csix_inv_state_machine port map(RxSOF => RxSOF_at2, RxData_type => RxData_at2(29 downto 26), RxData_info => temp_info2, RxData_type1 => RxData_type1,
			        counter_value_inv => counter_value_inv, output_sel_inv => output_sel_inv, count_inv => count_inv, clk => RxClk, rst => rst,
			        end_of_transmission => eot_at1, vpar_sel_inv => vpar_sel_inv);
 
 EOT_OUT_REG: one_bit_reg port map(q => eot_at2, rst => rst, clk => RxClk, d => eot_at1);
		
 EOT_OUT_REG1: one_bit_reg port map(q => end_of_transmission, rst => rst, clk => RxClk, d => eot_at2);
 
 RXDATA_TYPE_REG: four_bit_reg port map(q => RxData_type1, clk => RxClk, rst => rst, d => RxData_at2(29 downto 26));

 OSI0: one_bit_reg port map(q => output_sel_inv1(0), clk => RxClk, rst => rst, d => output_sel_inv(0));
 OSI1: one_bit_reg port map(q => output_sel_inv1(1), clk => RxClk, rst => rst, d => output_sel_inv(1));
 OSI2: one_bit_reg port map(q => output_sel_inv1(2), clk => RxClk, rst => rst, d => output_sel_inv(2));

 VSI0: one_bit_reg port map(q => vpar_sel_inv1(0), clk => RxClk, rst => rst, d => vpar_sel_inv(0));
 VSI1: one_bit_reg port map(q => vpar_sel_inv1(1), clk => RxClk, rst => rst, d => vpar_sel_inv(1));

 RXDATA_REG3: thirtytwo_bit_reg port map(q => RxData_at3, clk => RxClk, rst => rst, d => RxData_at2);

 CSIX_DATA_DECONSTRUCTOR_UNIT: csix_data_deconstructor port map(output_bus => output_bus_at1, input_bus => RxData_at3, output_sel_inv => output_sel_inv1, clk => RxClk, rst => rst);

 HORIZONTAL_PARITY_CHECK: horizontal_parity_generator_32bit port map(data => RxData_at3, TxPar => RxPar_check);

 VERTICAL_PARITY_FOR_RECEIVE: vertical_parity_generator port map(clk => RxClk, rst => rst, sel => vpar_sel_inv1, first16bit => RxData_at3(31 downto 16), second16bit => RxData_at3(15 downto 0), 
				prev_vpar => prev_vpar_inv); --current_vpar is not connected

 PREV_VPAR_INV_REG: sixteen_bit_reg port map(q => vpar_portion, clk => RxClk, rst => rst, d => RxData_at3(15 downto 0));				
  
 not_vpar_portion <= not(vpar_portion);
 after_xor(0) <= not_vpar_portion(0) xor prev_vpar_inv(0);
 after_xor(1) <= not_vpar_portion(1) xor prev_vpar_inv(1);
 after_xor(2) <= not_vpar_portion(2) xor prev_vpar_inv(2);
 after_xor(3) <= not_vpar_portion(3) xor prev_vpar_inv(3);
 after_xor(4) <= not_vpar_portion(4) xor prev_vpar_inv(4);
 after_xor(5) <= not_vpar_portion(5) xor prev_vpar_inv(5);
 after_xor(6) <= not_vpar_portion(6) xor prev_vpar_inv(6);
 after_xor(7) <= not_vpar_portion(7) xor prev_vpar_inv(7);
 after_xor(8) <= not_vpar_portion(8) xor prev_vpar_inv(8);
 after_xor(9) <= not_vpar_portion(9) xor prev_vpar_inv(9);
 after_xor(10) <= not_vpar_portion(10) xor prev_vpar_inv(10);
 after_xor(11) <= not_vpar_portion(11) xor prev_vpar_inv(11);
 after_xor(12) <= not_vpar_portion(12) xor prev_vpar_inv(12);
 after_xor(13) <= not_vpar_portion(13) xor prev_vpar_inv(13);
 after_xor(14) <= not_vpar_portion(14) xor prev_vpar_inv(14);
 after_xor(15) <= not_vpar_portion(15) xor prev_vpar_inv(15);
  
 bitwise_or_then_not <= not(after_xor(0) or after_xor(1)  or after_xor(2) or after_xor(3) or after_xor(4) or after_xor(5) or after_xor(6) or after_xor(7) or
                            after_xor(8) or after_xor(9)  or after_xor(10) or after_xor(11) or after_xor(12) or after_xor(13) or after_xor(14) or after_xor(15));
                             
 all_data_ok1 <= bitwise_or_then_not;

 ALL_DATA_OK_REG: one_bit_reg port map(q => all_data_ok, rst => rst, clk => RxClk, d => all_data_ok1);

 H_PAR_PROCESS: process(RxPar_at3, RxPar_check)
 begin
  if (RxPar_at3 = not(RxPar_check)) then
   h_par_at1 <= '1';
  else
   h_par_at1 <= '0';
  end if;  
 end process;

 H_PAR_AT2_REG: one_bit_reg port map(q => h_par_at2, rst => rst, clk => RxClk, d => h_par_at1);
		
 H_PAR_REG: one_bit_reg port map(q => h_par, rst => rst, clk => RxClk, d => h_par_at2);		 

 OUTPUT_BUS_OUT_REG: fortyfour_bit_reg port map(q => output_to_system, clk => RxClk, rst => rst, d => output_bus_at1);

end csix_behavior;

-----------------------------
-- CSIX Data Deconstructor --
-----------------------------


--This module takes in CSIX format 32-bit data received and
--convert it to the 44-bit format used in this implementation.

--Output Bus Data Format:
--
-- TYPE/BIT POS   43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
-- Idle         :| Type(4)   | Payload Length(8)     | Don't cares(32) also called DC                                                      |
-- Unicast      :| Type(4)   | Payload Length(8)     | Class(8)              | Destination Address(12)           | Don't Cares(12)         |
-- Multicast M. :| Type(4)   | Payload Length(8)     | Class(8)              | Bitmask Header(8)     | Bitmap(16)                          |
-- Multicast ID :| Type(4)   | Payload Length(8)     | Class(8)              | Multicast ID (22)                                       | DC|
-- Multicast Bin:| Type(4)   | Payload Length(8)     | Class(8)              | Left Destination Address(12)      | R. Destination Addr(12) |
-- Broadcast    :| Type(4)   | Payload Length(8)     | Class(8)              | Don't Cares(24)                                             |
-- Flow Control :| Type(4)   | Payload Length(8)     | Class(8)              | FCT | C| P| Speed(4)  | Destination Address(12)     | DC(4) |
-- Data         :| Don't Cares(12)                   | Data(32)                                                                            |


library ieee;
use ieee.std_logic_1164.all;
entity csix_data_deconstructor is
 port(clk, rst: in std_logic;
      output_bus: out std_logic_vector(43 downto 0);
      input_bus: in std_logic_vector(31 downto 0);
      output_sel_inv: in std_logic_vector(2 downto 0));
end csix_data_deconstructor;

architecture csix_data_deconstructor_behavior of csix_data_deconstructor is
component thirtytwo_bit_reg
 port(rst, clk: in std_logic;
      d:in std_logic_vector(31 downto 0); 
      q: out std_logic_vector(31 downto 0));
end component;
component fortyfour_bit_mux8_to_1
 port(sel: in std_logic_vector(2 downto 0);
      i0, i1, i2, i3, i4, i5, i6, i7: in std_logic_vector(43 downto 0);
      out_port: out std_logic_vector(43 downto 0));
end component;

signal byte1n2: std_logic_vector(31 downto 0);
signal idle_type, unicast_type, multicastm_type, multicastid_type, multicastbin_type, broadcast_type, flowcontrol_type, data_type: std_logic_vector(43 downto 0);

begin

 DELAYING_BYTE1N2: thirtytwo_bit_reg port map(q => byte1n2, clk => clk, rst => rst, d => input_bus);

 --Building the appropriate 44-bit data format from the input.
 idle_type <= (byte1n2(29 downto 26) & byte1n2(23 downto 16) & "00000000000000000000000000000000");
 unicast_type <= (byte1n2(29 downto 26) & byte1n2(23 downto 16) & byte1n2(15 downto 8) & input_bus(27 downto 16) & "000000000000");
 multicastm_type <= (byte1n2(29 downto 26) & byte1n2(23 downto 16) & byte1n2(15 downto 0) & input_bus(31 downto 16));
 multicastid_type <= (byte1n2(29 downto 26) & byte1n2(23 downto 16) & byte1n2(15 downto 8) & byte1n2(5 downto 0) & input_bus(31 downto 16) & "00");
 multicastbin_type <= (byte1n2(29 downto 26) & byte1n2(23 downto 0) & input_bus(31 downto 16));
 broadcast_type <= (byte1n2(29 downto 26) & byte1n2(23 downto 16) & byte1n2(15 downto 8) & "000000000000000000000000");
 flowcontrol_type <= (byte1n2(29 downto 26) & byte1n2(23 downto 16) & byte1n2(15 downto 0) & input_bus(27 downto 16) & "0000");
 data_type <= ("000000000000" & byte1n2(15 downto 0) & input_bus(31 downto 16));

 OUTPUT_BUS_MUX: fortyfour_bit_mux8_to_1 port map(out_port => output_bus, i0 => idle_type, i1 => unicast_type, i2 => multicastm_type, i3 => multicastid_type, i4 => multicastbin_type, i5 => broadcast_type, i6 => flowcontrol_type, i7 => data_type, sel => output_sel_inv);

end csix_data_deconstructor_behavior;

--------------------------------
-- CSIX Inverse State Machine --
--------------------------------


--This state machine controls the data flow and signals
--during receiving of data.

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity csix_inv_state_machine is
 port(clk, rst, RxSOF: in std_logic;
      RxData_type, RxData_type1: in std_logic_vector(3 downto 0);
      RxData_info, counter_value_inv: in std_logic_vector(8 downto 0);
      count_inv, end_of_transmission: out std_logic;
      vpar_sel_inv: out std_logic_vector(1 downto 0);
      output_sel_inv: out std_logic_vector(2 downto 0));
end csix_inv_state_machine;

architecture csix_inv_state_machine_behavior of csix_inv_state_machine is
signal count_inv_sig, end_of_transmission_sig: std_logic;
signal current_state, next_state, vpar_sel_inv_sig: std_logic_vector(1 downto 0);
signal output_sel_inv_sig: std_logic_vector(2 downto 0);
signal payload_num_received_preserver, payload_num_received: unsigned(8 downto 0);

begin

 SEQ: process(rst, clk)
 begin
  if (rst = '0') then
   current_state <= "00";
   payload_num_received_preserver <= "000000000";
  elsif (clk = '1' and clk'event) then
   current_state <= next_state;
   payload_num_received_preserver <= payload_num_received;
  end if;
 end process;
 
 PAYLOAD_NUM_RECEIVED_LOGIC: process(RxSOF, RxData_info, payload_num_received_preserver)
 begin 
  if (RxSOF = '0') then
   payload_num_received <= payload_num_received_preserver;
  elsif (RxSOF = '1') then
   payload_num_received <= UNSIGNED(RxData_info);
  end if;