csix_typer.vhd

Common Switch Interface CSIX-L1 Reference Design

 process(sel, i0, i1)
 begin
  case sel is
   when '0' =>
    out_port <= i0;
   when '1' =>
    out_port <= i1;
   when others =>
    out_port <= i0;  
  end case;
 end process;
end thirtytwo_bit_mux2_to_1_behavior;

----------------------------
-- Thirty-Two Bit 5:1 Mux --
----------------------------


library ieee;
use ieee.std_logic_1164.all;
entity thirtytwo_bit_mux5_to_1 is
 port(sel: in std_logic_vector(2 downto 0);
      i0, i1, i2, i3, i4: in std_logic_vector(31 downto 0);
      out_port: out std_logic_vector(31 downto 0));
end thirtytwo_bit_mux5_to_1;

architecture thirtytwo_bit_mux5_to_1_behavior of thirtytwo_bit_mux5_to_1 is
begin
 process(sel, i0, i1, i2, i3, i4)
 begin
  case sel is
   when "000" =>
    out_port <= i0;
   when "001" =>
    out_port <= i1;
   when "010" =>
    out_port <= i2;  
   when "011" =>
    out_port <= i3;  
   when "100" =>
    out_port <= i4;  
   when others =>
    out_port <= i0;  
  end case;
 end process;
end thirtytwo_bit_mux5_to_1_behavior;

-------------------------
-- Sixteen Bit 6:1 Mux --
-------------------------


-- This mux is designed for and unique to this CSIX implementation

library ieee;
use ieee.std_logic_1164.all;
entity sixteen_bit_mux6_to_1 is
 port(sel: in std_logic_vector(2 downto 0);
      i1, i2, i3, i4, i5, i6: in std_logic_vector(15 downto 0);
      out_port: out std_logic_vector(15 downto 0));
end sixteen_bit_mux6_to_1;

architecture sixteen_bit_mux6_to_1_behavior of sixteen_bit_mux6_to_1 is
begin
 process(sel, i1, i2, i3, i4, i5, i6)
 begin
  case sel is
   when "001" =>
    out_port <= i1;
   when "010" =>
    out_port <= i2;  
   when "011" =>
    out_port <= i3;  
   when "100" =>
    out_port <= i4;  
   when "101" =>
    out_port <= i5;  
   when "110" =>
    out_port <= i6;  
   when others =>
    out_port <= i1;  
  end case;
 end process;
end sixteen_bit_mux6_to_1_behavior;

-----------------------
-- Four Bit Register --
-----------------------


library ieee;
use ieee.std_logic_1164.all;
entity four_bit_reg is
 port(rst, clk:in std_logic; 
      d:in std_logic_vector(3 downto 0); 
      q: out std_logic_vector(3 downto 0));
end four_bit_reg;

architecture four_bit_reg_behavior of four_bit_reg is
begin
 process(rst, clk)
 begin
  if (rst = '0') then
   q <= "0000";
  elsif (clk = '1' and clk'event) then
   q <= d;
  end if;
 end process;
end four_bit_reg_behavior;

-----------------------------
-- Forty-Four Bit Register --
-----------------------------


library ieee;
use ieee.std_logic_1164.all;
entity fortyfour_bit_reg is
 port(rst, clk: in std_logic;
      d:in std_logic_vector(43 downto 0); 
      q: out std_logic_vector(43 downto 0));
end fortyfour_bit_reg;

architecture fortyfour_bit_reg_behavior of fortyfour_bit_reg is
begin
 process(rst, clk)
 begin
  if (rst = '0') then
   q <= "00000000000000000000000000000000000000000000";
  elsif (clk = '1' and clk'event) then
   q <= d;
  end if;
 end process;
end fortyfour_bit_reg_behavior;

------------------------------
-- Forty-Eight Bit Register --
------------------------------


library ieee;
use ieee.std_logic_1164.all;
entity fortyeight_bit_reg is
 port(rst, clk: in std_logic;
      d:in std_logic_vector(47 downto 0); 
      q: out std_logic_vector(47 downto 0));
end fortyeight_bit_reg;

architecture fortyeight_bit_reg_behavior of fortyeight_bit_reg is
begin
 process(rst, clk)
 begin
  if (rst = '0') then
   q <= "000000000000000000000000000000000000000000000000";
  elsif (clk = '1' and clk'event) then
   q <= d;
  end if;
 end process;
end fortyeight_bit_reg_behavior;

-----------------------------
-- Thirty-Two Bit Register --
-----------------------------


library ieee;
use ieee.std_logic_1164.all;
entity thirtytwo_bit_reg is
 port(rst, clk: in std_logic;
      d:in std_logic_vector(31 downto 0); 
      q: out std_logic_vector(31 downto 0));
end thirtytwo_bit_reg;

architecture thirtytwo_bit_reg_behavior of thirtytwo_bit_reg is
begin
 process(rst, clk)
 begin
  if (rst = '0') then
   q <= "00000000000000000000000000000000";
  elsif (clk = '1' and clk'event) then
   q <= d;
  end if;
 end process;
end thirtytwo_bit_reg_behavior;

--------------------------
-- Sixteen Bit Register --
--------------------------


library ieee;
use ieee.std_logic_1164.all;
entity sixteen_bit_reg is
 port(rst, clk: in std_logic;
      d:in std_logic_vector(15 downto 0); 
      q: out std_logic_vector(15 downto 0));
end sixteen_bit_reg;

architecture sixteen_bit_reg_behavior of sixteen_bit_reg is
begin
 process(rst, clk)
 begin
  if (rst = '0') then
   q <= "0000000000000000";
  elsif (clk = '1' and clk'event) then
   q <= d;
  end if;
 end process;
end sixteen_bit_reg_behavior;

----------------------
-- One Bit Register --
----------------------


library ieee;
use ieee.std_logic_1164.all;
entity one_bit_reg is
 port(rst, clk, d:in std_logic; 
      q: out std_logic);
end one_bit_reg;

architecture one_bit_reg_behavior of one_bit_reg is
begin
 process(rst, clk)
 begin
  if (rst = '0') then
   q <= '0';
  elsif (clk = '1' and clk'event) then
   q <= d;
  end if;
 end process;
end one_bit_reg_behavior;

------------------
-- Count To 256 --
------------------


--This block counts from 0 to 511, and used in
--CSIX to keep track the number of bytes being
--received or transmitted.

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity count_to_256 is
 port(clk, rst, count: in std_logic;
      counter_value: out std_logic_vector(8 downto 0));
end count_to_256;

architecture count_to_256_behavior of count_to_256 is
signal counter_value_sig, counter_value_preserver: unsigned(8 downto 0);
begin

 process(count, counter_value_preserver)
 begin
  if (count = '0') then
   counter_value_sig <=  "000000000";
  elsif (count = '1') then
   counter_value_sig <= counter_value_preserver + "000000100";
  end if;
 end process;
 
 process(clk, rst)
 begin
  if (rst = '0') then
   counter_value_preserver <= "000000000";
  elsif (clk = '1' and clk'event) then
   counter_value_preserver <= counter_value_sig;
  end if;
 end process;
 
 counter_value <= STD_LOGIC_VECTOR(counter_value_sig);
end count_to_256_behavior;

---------------------------------
-- Horizontal Parity Generator --
---------------------------------


library ieee;
use ieee.std_logic_1164.all;
entity horizontal_parity_generator_32bit is
 port(data:in std_logic_vector(31 downto 0); 
      TxPar: out std_logic);
end horizontal_parity_generator_32bit;

architecture horizontal_parity_generator_32bit_behavior of horizontal_parity_generator_32bit is
begin
 process(data)
 begin
  TxPar <= data(0) xor data(1) xor data(2) xor data(3) xor data(4) xor data(5) xor data(6) xor data(7) xor data(8) xor data(9) xor
           data(10) xor data(11) xor data(12) xor data(13) xor data(14) xor data(15) xor data(16) xor data(17) xor data(18) xor data(19) xor
           data(20) xor data(21) xor data(22) xor data(23) xor data(24) xor data(25) xor data(26) xor data(27) xor data(28) xor data(29) xor
           data(30) xor data(31);
 end process;
end horizontal_parity_generator_32bit_behavior;

-------------------------------
-- Vertical Parity Generator --
-------------------------------


library ieee;
use ieee.std_logic_1164.all;
entity vertical_parity_generator is
 port(clk, rst: in std_logic;
      sel: in std_logic_vector(1 downto 0);
      first16bit, second16bit:in std_logic_vector(15 downto 0); 
      current_vpar, prev_vpar: out std_logic_vector(15 downto 0));
end vertical_parity_generator;

architecture vertical_parity_generator_behavior of vertical_parity_generator is
component sixteen_bit_reg
 port(rst, clk: in std_logic;
      d:in std_logic_vector(15 downto 0); 
      q: out std_logic_vector(15 downto 0));
end component;
signal current_vpar_sig, prev_vpar_sig : std_logic_vector(15 downto 0);

begin 
 SIXTEEN_BIT_REG_FOR_PREV_VPAR: sixteen_bit_reg port map(rst => rst, clk => clk, d => current_vpar_sig, q => prev_vpar_sig);

 process(first16bit, second16bit, sel, prev_vpar_sig)
 begin
  case sel is
   when "00" =>
    current_vpar_sig <= "0000000000000000";
   when "01" =>
    current_vpar_sig <= first16bit xor second16bit;
   when "10" =>
    current_vpar_sig <= prev_vpar_sig xor first16bit xor second16bit;
   when "11" =>
    current_vpar_sig <= prev_vpar_sig xor first16bit;
   when others =>
    current_vpar_sig <= "0000000000000000";  
  end case;
 end process;
 
 current_vpar <= current_vpar_sig;
 prev_vpar <= prev_vpar_sig;
end vertical_parity_generator_behavior;

----------------------------
-- Forty-Four Bit 8:1 Mux --
----------------------------


library ieee;
use ieee.std_logic_1164.all;
entity fortyfour_bit_mux8_to_1 is
 port(sel: in std_logic_vector(2 downto 0);
      i0, i1, i2, i3, i4, i5, i6, i7: in std_logic_vector(43 downto 0);
      out_port: out std_logic_vector(43 downto 0));
end fortyfour_bit_mux8_to_1;

architecture fortyfour_bit_mux8_to_1_behavior of fortyfour_bit_mux8_to_1 is
begin
 process(sel, i0, i1, i2, i3, i4, i5, i6, i7)
 begin
  case sel is
   when "000" =>
    out_port <= i0;
   when "001" =>
    out_port <= i1;
   when "010" =>
    out_port <= i2;  
   when "011" =>
    out_port <= i3;  
   when "100" =>
    out_port <= i4;  
   when "101" =>
    out_port <= i5;  
   when "110" =>
    out_port <= i6;  
   when "111" =>
    out_port <= i7;      
   when others =>
    out_port <= i0;  
  end case;
 end process;
end fortyfour_bit_mux8_to_1_behavior;