csix_test.v

Common Switch Interface CSIX-L1 Reference Design

`timescale 1ns/100ps

module test;

parameter CLOCK_CYCLE = 10; //Works best if it's an integer
//some simulators have difficulties with mathematical operands of clock.
//THis clock cycle is the suggested value.

reg clk, rst;
reg [43:0] input_bus, input_bus1;
reg inst_signal, inst_signal1;

wire [31:0] TxData;
wire [31:0] RxData;
wire TxSOF, get_inst, get_inst1, TxPar, RxPar, RxSOF, start_of_received;
wire [43:0] output_to_system1;
wire eot, h_par, ado, TxClk;
wire [43:0] output_to_system;
wire sot1, eot1, h_par1, ado1;

csix csix_unit(
	.clk(clk),
	.rst(rst),
	.input_bus(input_bus),
	.output_to_system(output_to_system),
	.inst_signal(inst_signal),
	.RxData(RxData),
	.RxPar(RxPar),
	.RxSOF(RxSOF),
	.RxClk(RxClk),
	.TxData(TxData),
	.TxPar(TxPar),
	.TxSOF(TxSOF),
	.TxClk(TxClk),	
	.get_inst(get_inst),	
	.start_of_received(sot1),
	.end_of_transmission(eot1),
	.h_par(h_par1),
	.all_data_ok(ado1)
	);

csix csix_unit1(
	.clk(clk),
	.rst(rst),
	.input_bus(input_bus1),
	.output_to_system(output_to_system1),
	.inst_signal(inst_signal1),
	.RxData(TxData),
	.RxPar(TxPar),
	.RxSOF(TxSOF),
	.RxClk(TxClk),
	.TxData(RxData),
	.TxPar(RxPar),
	.TxSOF(RxSOF),
	.TxClk(RxClk),
	.get_inst(get_inst1),
	.start_of_received(start_of_received),
	.end_of_transmission(eot),
	.h_par(h_par),
	.all_data_ok(ado)
	);




initial
begin
 input_bus = 44'h000_0000_0000;
 input_bus1 = 44'h000_0000_0000;
 //input_bus = 44'h101_2345_6DDD; 
 //input_bus = 44'h102_2345_6DDD; 
 //input_bus = 44'h103_2345_6DDD; 
 //input_bus = 44'h104_2345_6DDD; 
 //input_bus = 44'h105_2345_6DDD; 
 //input_bus = 44'h106_2345_6DDD; 
 //input_bus = 44'h107_2345_6DDD; 
 //input_bus = 44'h108_2345_6DDD; 
 //input_bus = 44'h109_2345_6DDD; 
 //input_bus = 44'h10A_2345_6DDD; 
 //input_bus = 44'h10B_2345_6DDD; 
 //input_bus = 44'h10C_2345_6DDD; 
 //input_bus = 44'h10D_2345_6DDD; 
 //input_bus = 44'h10E_2345_6DDD; 
 //input_bus = 44'h10F_2345_6DDD; 
 //input_bus = 44'h110_2345_6DDD; 
 //input_bus = 44'h111_2345_6DDD; 
 //input_bus = 44'h112_2345_6DDD; 
 //input_bus = 44'h113_2345_6DDD;
 //input_bus = 44'h114_2345_6DDD;
 //input_bus = 44'h100_2345_6DDD;
 //RxData = 32'hC000_0000;
 inst_signal = 1'b0;
 inst_signal1 = 1'b0;
 clk = 1'b1;
 rst = 1'b1;
end	

 
always
 #(CLOCK_CYCLE/2.0) clk = ~clk;

initial
begin
#(0.3*CLOCK_CYCLE) rst = 1'b0;
#(0.3*CLOCK_CYCLE) rst = 1'b1;
//#(2.7*CLOCK_CYCLE) inst_signal = 1'b1; input_bus = 44'h10C_2345_6DDD; 
//#(4.7*CLOCK_CYCLE) inst_signal = 1'b1; input_bus = 44'h10C_2345_6DDD; 
#(7.7*CLOCK_CYCLE) inst_signal = 1'b1; input_bus = 44'h10B_2345_6DDD;
inst_signal1 = 1'b1; input_bus1 = 44'h10B_2345_6DDD;
#CLOCK_CYCLE inst_signal = 1'b0; input_bus = 44'h000_0102_0304;
inst_signal1 = 1'b0; input_bus1 = 44'h001_1102_0304;
#CLOCK_CYCLE input_bus = 44'h000_0506_0708;
input_bus1 = 44'h001_1506_0708;
#CLOCK_CYCLE input_bus = 44'h000_090A_0B0C;
input_bus1 = 44'h001_190A_0B0C;
#CLOCK_CYCLE input_bus = 44'h000_0000_0000;
input_bus1 = 44'h000_0000_0000;
#CLOCK_CYCLE input_bus = 44'h101_2345_6DDD; inst_signal = 1'b1;
input_bus1 = 44'h101_2345_6DDD; inst_signal1 = 1'b1;
#CLOCK_CYCLE input_bus = 44'h000_0D0E_0F10; inst_signal = 1'b0;
input_bus1 = 44'h001_1D0E_0F10; inst_signal1 = 1'b0;
#CLOCK_CYCLE input_bus = 44'hFFF_FFFF_FFFF;
input_bus1 = 44'hFFF_FFFF_FFFF;
#CLOCK_CYCLE input_bus = 44'h103_2345_6DDD; inst_signal = 1'b1;
input_bus1 = 44'h103_2345_6DDD; inst_signal1 = 1'b1;
#CLOCK_CYCLE input_bus = 44'h000_1112_1314; inst_signal = 1'b0;
input_bus1 = 44'h000_1112_1314; inst_signal1 = 1'b0;
#CLOCK_CYCLE input_bus = 44'h000_1516_1718;
input_bus1 = 44'h000_1516_1718;
//#CLOCK_CYCLE inst_signal = 1'b1; input_bus = 44'h10C_2345_6DDD;
//#(4*CLOCK_CYCLE) inst_signal = 1'b1; input_bus = 44'h10C_2345_6DDD;
#(24*CLOCK_CYCLE) inst_signal = 1'b1; input_bus = 44'h100_2345_6DDD;
inst_signal1 = 1'b1; input_bus1 = 44'h100_2345_6DDD; 
#CLOCK_CYCLE inst_signal = 1'b0; input_bus = 44'h000_0102_0304;
inst_signal1 = 1'b0; input_bus1 = 44'h001_1102_0304;
#CLOCK_CYCLE input_bus = 44'h000_0506_0708;
input_bus1 = 44'h001_1506_0708;
#CLOCK_CYCLE input_bus = 44'h000_090A_0B0C;
input_bus1 = 44'h001_190A_0B0C;
#CLOCK_CYCLE input_bus = 44'h000_0D0E_0F10;
input_bus1 = 44'h001_1D0E_0F10;
#CLOCK_CYCLE input_bus = 44'h000_0102_0304;
input_bus1 = 44'h001_1102_0304;
#CLOCK_CYCLE input_bus = 44'h000_0506_0708;
input_bus1 = 44'h001_1506_0708;
#CLOCK_CYCLE input_bus = 44'h000_090A_0B0C;
input_bus1 = 44'h001_190A_0B0C;
#CLOCK_CYCLE input_bus = 44'h000_0D0E_0F11;
input_bus1 = 44'h001_1D0E_0F11;
#CLOCK_CYCLE input_bus = 44'h000_0102_0304;
input_bus1 = 44'h001_1102_0304;
#CLOCK_CYCLE input_bus = 44'h000_0506_0708;
input_bus1 = 44'h001_1506_0708;
#CLOCK_CYCLE input_bus = 44'h000_090A_0B0C;
input_bus1 = 44'h001_190A_0B0C;
#CLOCK_CYCLE input_bus = 44'h000_0D0E_0F12;
input_bus1 = 44'h001_1D0E_0F12;
#CLOCK_CYCLE input_bus = 44'h000_0102_0304;
input_bus1 = 44'h001_1102_0304;
#CLOCK_CYCLE input_bus = 44'h000_0506_0708;
input_bus1 = 44'h001_1506_0708;
#CLOCK_CYCLE input_bus = 44'h000_090A_0B0C;
input_bus1 = 44'h001_190A_0B0C;
#CLOCK_CYCLE input_bus = 44'h000_0D0E_0F13;
input_bus1 = 44'h001_1D0E_0F13;
#CLOCK_CYCLE input_bus = 44'h000_0102_0304;
input_bus1 = 44'h001_1102_0304;
#CLOCK_CYCLE input_bus = 44'h000_0506_0708;
input_bus1 = 44'h001_1506_0708;
#CLOCK_CYCLE input_bus = 44'h000_090A_0B0C;
input_bus1 = 44'h001_190A_0B0C;
#CLOCK_CYCLE input_bus = 44'h000_0D0E_0F14;
input_bus1 = 44'h001_1D0E_0F14;
#CLOCK_CYCLE input_bus = 44'h000_0102_0304;
input_bus1 = 44'h001_1102_0304;
#CLOCK_CYCLE input_bus = 44'h000_0506_0708;
input_bus1 = 44'h001_1506_0708;
#CLOCK_CYCLE input_bus = 44'h000_090A_0B0C;
input_bus1 = 44'h001_190A_0B0C;
#CLOCK_CYCLE input_bus = 44'h000_0D0E_0F15;
input_bus1 = 44'h001_1D0E_0F15;
#CLOCK_CYCLE input_bus = 44'h000_0102_0304;
input_bus1 = 44'h001_1102_0304;
#CLOCK_CYCLE input_bus = 44'h000_0506_0708;
input_bus1 = 44'h001_1506_0708;
#CLOCK_CYCLE input_bus = 44'h000_090A_0B0C;
input_bus1 = 44'h001_190A_0B0C;
#CLOCK_CYCLE input_bus = 44'h000_0D0E_0F16;
input_bus1 = 44'h001_1D0E_0F16;
#CLOCK_CYCLE input_bus = 44'h000_0102_0304;
input_bus1 = 44'h001_1102_0304;
#CLOCK_CYCLE input_bus = 44'h000_0506_0708;
input_bus1 = 44'h001_1506_0708;
#CLOCK_CYCLE input_bus = 44'h000_090A_0B0C;
input_bus1 = 44'h001_190A_0B0C;
#CLOCK_CYCLE input_bus = 44'h000_0D0E_0F17;
input_bus1 = 44'h001_1D0E_0F17;
#CLOCK_CYCLE input_bus = 44'h000_0102_0304;
input_bus1 = 44'h001_1102_0304;
#CLOCK_CYCLE input_bus = 44'h000_0506_0708;
input_bus1 = 44'h001_1506_0708;
#CLOCK_CYCLE input_bus = 44'h000_090A_0B0C;
input_bus1 = 44'h001_190A_0B0C;
#CLOCK_CYCLE input_bus = 44'h000_0D0E_0F18;
input_bus1 = 44'h001_1D0E_0F18;
#CLOCK_CYCLE input_bus = 44'h000_0102_0304;
input_bus1 = 44'h001_1102_0304;
#CLOCK_CYCLE input_bus = 44'h000_0506_0708;
input_bus1 = 44'h001_1506_0708;
#CLOCK_CYCLE input_bus = 44'h000_090A_0B0C;
input_bus1 = 44'h001_190A_0B0C;
#CLOCK_CYCLE input_bus = 44'h000_0D0E_0F19;
input_bus1 = 44'h001_1D0E_0F19;
#CLOCK_CYCLE input_bus = 44'h000_0102_0304;
input_bus1 = 44'h001_1102_0304;
#CLOCK_CYCLE input_bus = 44'h000_0506_0708;
input_bus1 = 44'h001_1506_0708;
#CLOCK_CYCLE input_bus = 44'h000_090A_0B0C;
input_bus1 = 44'h001_190A_0B0C;
#CLOCK_CYCLE input_bus = 44'h000_0D0E_0F1A;
input_bus1 = 44'h001_1D0E_0F1A;
#CLOCK_CYCLE input_bus = 44'h000_0102_0304;
input_bus1 = 44'h001_1102_0304;
#CLOCK_CYCLE input_bus = 44'h000_0506_0708;
input_bus1 = 44'h001_1506_0708;
#CLOCK_CYCLE input_bus = 44'h000_090A_0B0C;
input_bus1 = 44'h001_190A_0B0C;
#CLOCK_CYCLE input_bus = 44'h000_0D0E_0F1B;
input_bus1 = 44'h001_1D0E_0F1B;
#CLOCK_CYCLE input_bus = 44'h000_0102_0304;
input_bus1 = 44'h001_1102_0304;
#CLOCK_CYCLE input_bus = 44'h000_0506_0708;
input_bus1 = 44'h001_1506_0708;
#CLOCK_CYCLE input_bus = 44'h000_090A_0B0C;
input_bus1 = 44'h001_190A_0B0C;
#CLOCK_CYCLE input_bus = 44'h000_0D0E_0F1C;
input_bus1 = 44'h001_1D0E_0F1C;
#CLOCK_CYCLE input_bus = 44'h000_0102_0304;
input_bus1 = 44'h001_1102_0304;
#CLOCK_CYCLE input_bus = 44'h000_0506_0708;
input_bus1 = 44'h001_1506_0708;
#CLOCK_CYCLE input_bus = 44'h000_090A_0B0C;
input_bus1 = 44'h001_190A_0B0C;
#CLOCK_CYCLE input_bus = 44'h000_0D0E_0F1D;
input_bus1 = 44'h001_1D0E_0F1D;
#CLOCK_CYCLE input_bus = 44'h000_0102_0304;
input_bus1 = 44'h001_1102_0304;
#CLOCK_CYCLE input_bus = 44'h000_0506_0708;
input_bus1 = 44'h001_1506_0708;
#CLOCK_CYCLE input_bus = 44'h000_090A_0B0C;
input_bus1 = 44'h001_190A_0B0C;
#CLOCK_CYCLE input_bus = 44'h000_0D0E_0F1E;
input_bus1 = 44'h001_1D0E_0F1E;
#CLOCK_CYCLE input_bus = 44'h000_0102_0304;
input_bus1 = 44'h001_1102_0304;
#CLOCK_CYCLE input_bus = 44'h000_0506_0708;
input_bus1 = 44'h001_1506_0708;
#CLOCK_CYCLE input_bus = 44'h000_090A_0B0C;
input_bus1 = 44'h001_190A_0B0C;
#CLOCK_CYCLE input_bus = 44'h000_0D0E_0F1F;
input_bus1 = 44'h001_1D0E_0F1F;
#CLOCK_CYCLE input_bus = 44'h000_0000_0001;
input_bus1 = 44'h000_0000_0001;
#1000 $finish;
end


endmodule