!readme.txt

Common Switch Interface CSIX-L1 Reference Design

Tools used:

Device: 2V1000 -5
Simulator: Modeltech Modelsim 5.5c
Synthesis: Synplicity Synplify 6.2.4
Place and Route: Design Manager 3.3.06i (part of Foundation ISE 3.3i)
Utilization 360 slices, 166 IOB
Max Speed: 166 MHz

Device: 2VP7 -6
Simulator: Modeltech Modelsim 5.5c
Synthesis: Synplicity Synplify 7.0.3
Place and Route: Design Manager 4.2i (part of Foundation ISE 4.2i)
Utilization: 342 slices, 166 IOB
Max Speed: 180 Mhz

Files:

csix.v/csix.vhd : original code version.
csix_typeR.v/csix_typeR.vhd : faster code version (uses one hot FSM encoding).
csix_test.v/csix_test.vhd: instantiations and demonstration of csix interface.

To run the test, used a simulator and view all the signals in csix_test.v/csix_test.vhd

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In this example (csix_test.v), we used two CSIX interface talking to each other. This illustration is similar to forward and inverse transform, in other words, whatever is going in will be recovered in the output.

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Transmitting Side:
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The system will set up itself upon power-up and reset according to the state machine provided in the CSIX documentation. Once it is ready, this system will ask for instruction by asserting get_inst signal to HIGH.

When idling, the system will send out an idle CFrame followed by dead-cycles periodically. At this mode, the get_inst signal will be asserted HIGH periodically.

When get_inst is asserted HIGH, the CSIX master may or may not provide 44-bit instructions. The instructions must be provided shortly after get_inst is asserted HIGH. This instruction will be sampled into the pipeline in the following clock cycle. The format of the 44-bit instructions is located in the data_constructor module. In addition, the master must provide an assert HIGH on inst_signal input line to indicate that the 44-bits are instructions bits. In the following clock cycles, 32-bit data is followed by the 44-bit instruction. The master should provide the correct number of data.

Data transmitted (TxData) across CSIX fabric appears 4-clock cycles after it is placed in the input.

In the test bench, the 44 bit signal is input_bus, while the Tx buses are TxData, TxPar, TxClk, and TxSOF.

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Receiving Side:
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The received data (RxData) on the receiver side is converted from 32-bit CSIX CFrame format to 44-bit format from the transmitting side. The output appears 5-clock cycles after the input is received.

On the receive-side beginning of signal is specified when the start_of_received signal is asserted high. Transmission completion is indicated when end_of_transmission (or eot) is asserted HIGH. Along with these signals, vertical and horizontal parity is indicated by signals called all_data_ok and horizontal parity.

During idling, start_of_received signal is periodically asserted HIGH, while end_of_transmission is asserted low.

In the test bench the 44-bit output is output_to_system.