csix_test.vhd

Common Switch Interface CSIX-L1 Reference Design

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

----------------
-- Test Bench --
----------------

--parameter CLOCK_CYCLE <= 10; --Works best if it's an integer
--some simulators have difficulties with mathematical operands of clock.
--This clock cycle is the suggested value.

entity test_bench is
end test_bench;

use work.all;
architecture behavior of test_bench is
component csix
 port(clk, rst, RxPar, RxSOF, RxClk, inst_signal: in std_logic;
      RxData: in std_logic_vector(31 downto 0);
      input_bus:in std_logic_vector(43 downto 0);
      TxPar, TxSOF, TxClk, get_inst, start_of_received, end_of_transmission, h_par, all_data_ok: out std_logic;
      TxData: out std_logic_vector(31 downto 0);
      output_to_system: out std_logic_vector(43 downto 0));
end component;

signal clk, rst: std_logic;
signal input_bus, input_bus1: std_logic_vector(43 downto 0);
signal inst_signal, inst_signal1: std_logic;

signal TxData: std_logic_vector(31 downto 0);
signal RxData: std_logic_vector(31 downto 0);
signal TxSOF, get_inst, get_inst1, TxPar, RxPar, RxSOF, start_of_received: std_logic;
signal output_to_system1: std_logic_vector(43 downto 0);
signal eot, h_par, ado, TxClk, RxClk: std_logic;
signal output_to_system: std_logic_vector(43 downto 0);
signal sot1, eot1, h_par1, ado1: std_logic;

begin
 csix_unit: csix port map(
	clk => clk,
	rst => rst,
	input_bus => input_bus,
	output_to_system => output_to_system,
	inst_signal => inst_signal,
	RxData => RxData,
	RxPar => RxPar,
	RxSOF => RxSOF,
	RxClk => RxClk,
	TxData => TxData,
	TxPar => TxPar,
	TxSOF => TxSOF,
	TxClk => TxClk,	
	get_inst => get_inst,
	start_of_received => sot1,
	end_of_transmission => eot1,
	h_par => h_par1,
	all_data_ok => ado1
	);

 csix_unit1: csix port map(
	clk => clk,
	rst => rst,
	input_bus => input_bus1,
	output_to_system => output_to_system1,
	inst_signal => inst_signal1,
	RxData => TxData,
	RxPar => TxPar,
	RxSOF => TxSOF,
	RxClk => TxClk,
	TxData => RxData,
	TxPar => RxPar,
	TxSOF => RxSOF,
	TxClk => RxClk,
	get_inst => get_inst1,
	start_of_received => start_of_received,
	end_of_transmission => eot,
	h_par => h_par,
	all_data_ok => ado
	);

clock: process
 variable clktmp: std_logic := '1';
 begin
  clktmp := not clktmp;
  clk <= clktmp;
  wait for 5 ns;
end process;

stimulus: process
begin
input_bus <= x"000_0000_0000";
input_bus1 <= x"000_0000_0000";
--input_bus <= x"101_2345_6DDD"; 
--input_bus <= x"102_2345_6DDD"; 
--input_bus <= x"103_2345_6DDD"; 
--input_bus <= x"104_2345_6DDD"; 
--input_bus <= x"105_2345_6DDD"; 
--input_bus <= x"106_2345_6DDD"; 
--input_bus <= x"107_2345_6DDD"; 
--input_bus <= x"108_2345_6DDD"; 
--input_bus <= x"109_2345_6DDD"; 
--input_bus <= x"10A_2345_6DDD"; 
--input_bus <= x"10B_2345_6DDD"; 
--input_bus <= x"10C_2345_6DDD"; 
--input_bus <= x"10D_2345_6DDD"; 
--input_bus <= x"10E_2345_6DDD"; 
--input_bus <= x"10F_2345_6DDD"; 
--input_bus <= x"110_2345_6DDD"; 
--input_bus <= x"111_2345_6DDD"; 
--input_bus <= x"112_2345_6DDD"; 
--input_bus <= x"113_2345_6DDD";
--input_bus <= x"114_2345_6DDD";
--input_bus <= x"100_2345_6DDD";
--RxData <= x"C000_0000";
 inst_signal <= '0';
 inst_signal1 <= '0';
 rst <= '1';
wait for 3 ns; 
rst <= '0';
wait for 3 ns; rst <= '1';
--wait for 27 ns; inst_signal <= '1'; input_bus <= x"10C_2345_6DDD"; 
--wait for 47 ns; inst_signal <= '1'; input_bus <= x"10C_2345_6DDD"; 
wait for 77 ns; inst_signal <= '1'; input_bus <= x"10B_2345_6DDD";
inst_signal1 <= '1'; input_bus1 <= x"10B_2345_6DDD";
wait for 10 ns; inst_signal <= '0'; input_bus <= x"000_0102_0304";
inst_signal1 <= '0'; input_bus1 <= x"001_1102_0304";
wait for 10 ns; input_bus <= x"000_0506_0708";
input_bus1 <= x"001_1506_0708";
wait for 10 ns; input_bus <= x"000_090A_0B0C";
input_bus1 <= x"001_190A_0B0C";
wait for 10 ns; input_bus <= x"000_0000_0000";
input_bus1 <= x"000_0000_0000";
wait for 10 ns; input_bus <= x"101_2345_6DDD"; inst_signal <= '1';
input_bus1 <= x"101_2345_6DDD"; inst_signal1 <= '1';
wait for 10 ns; input_bus <= x"000_0D0E_0F10"; inst_signal <= '0';
input_bus1 <= x"001_1D0E_0F10"; inst_signal1 <= '0';
wait for 10 ns; input_bus <= x"FFF_FFFF_FFFF";
input_bus1 <= x"FFF_FFFF_FFFF";
wait for 10 ns; input_bus <= x"103_2345_6DDD"; inst_signal <= '1';
input_bus1 <= x"103_2345_6DDD"; inst_signal1 <= '1';
wait for 10 ns; input_bus <= x"000_1112_1314"; inst_signal <= '0';
input_bus1 <= x"000_1112_1314"; inst_signal1 <= '0';
wait for 10 ns; input_bus <= x"000_1516_1718";
input_bus1 <= x"000_1516_1718";
--wait for 10 ns; inst_signal <= '1'; input_bus <= x"10C_2345_6DDD";
--wait for 40 ns; inst_signal <= '1'; input_bus <= x"10C_2345_6DDD";
wait for 240 ns; inst_signal <= '1'; input_bus <= x"100_2345_6DDD";
inst_signal1 <= '1'; input_bus1 <= x"100_2345_6DDD"; 
wait for 10 ns; inst_signal <= '0'; input_bus <= x"000_0102_0304";
inst_signal1 <= '0'; input_bus1 <= x"001_1102_0304";
wait for 10 ns; input_bus <= x"000_0506_0708";
input_bus1 <= x"001_1506_0708";
wait for 10 ns; input_bus <= x"000_090A_0B0C";
input_bus1 <= x"001_190A_0B0C";
wait for 10 ns; input_bus <= x"000_0D0E_0F10";
input_bus1 <= x"001_1D0E_0F10";
wait for 10 ns; input_bus <= x"000_0102_0304";
input_bus1 <= x"001_1102_0304";
wait for 10 ns; input_bus <= x"000_0506_0708";
input_bus1 <= x"001_1506_0708";
wait for 10 ns; input_bus <= x"000_090A_0B0C";
input_bus1 <= x"001_190A_0B0C";
wait for 10 ns; input_bus <= x"000_0D0E_0F11";
input_bus1 <= x"001_1D0E_0F11";
wait for 10 ns; input_bus <= x"000_0102_0304";
input_bus1 <= x"001_1102_0304";
wait for 10 ns; input_bus <= x"000_0506_0708";
input_bus1 <= x"001_1506_0708";
wait for 10 ns; input_bus <= x"000_090A_0B0C";
input_bus1 <= x"001_190A_0B0C";
wait for 10 ns; input_bus <= x"000_0D0E_0F12";
input_bus1 <= x"001_1D0E_0F12";
wait for 10 ns; input_bus <= x"000_0102_0304";
input_bus1 <= x"001_1102_0304";
wait for 10 ns; input_bus <= x"000_0506_0708";
input_bus1 <= x"001_1506_0708";
wait for 10 ns; input_bus <= x"000_090A_0B0C";
input_bus1 <= x"001_190A_0B0C";
wait for 10 ns; input_bus <= x"000_0D0E_0F13";
input_bus1 <= x"001_1D0E_0F13";
wait for 10 ns; input_bus <= x"000_0102_0304";
input_bus1 <= x"001_1102_0304";
wait for 10 ns; input_bus <= x"000_0506_0708";
input_bus1 <= x"001_1506_0708";
wait for 10 ns; input_bus <= x"000_090A_0B0C";
input_bus1 <= x"001_190A_0B0C";
wait for 10 ns; input_bus <= x"000_0D0E_0F14";
input_bus1 <= x"001_1D0E_0F14";
wait for 10 ns; input_bus <= x"000_0102_0304";
input_bus1 <= x"001_1102_0304";
wait for 10 ns; input_bus <= x"000_0506_0708";
input_bus1 <= x"001_1506_0708";
wait for 10 ns; input_bus <= x"000_090A_0B0C";
input_bus1 <= x"001_190A_0B0C";
wait for 10 ns; input_bus <= x"000_0D0E_0F15";
input_bus1 <= x"001_1D0E_0F15";
wait for 10 ns; input_bus <= x"000_0102_0304";
input_bus1 <= x"001_1102_0304";
wait for 10 ns; input_bus <= x"000_0506_0708";
input_bus1 <= x"001_1506_0708";
wait for 10 ns; input_bus <= x"000_090A_0B0C";
input_bus1 <= x"001_190A_0B0C";
wait for 10 ns; input_bus <= x"000_0D0E_0F16";
input_bus1 <= x"001_1D0E_0F16";
wait for 10 ns; input_bus <= x"000_0102_0304";
input_bus1 <= x"001_1102_0304";
wait for 10 ns; input_bus <= x"000_0506_0708";
input_bus1 <= x"001_1506_0708";
wait for 10 ns; input_bus <= x"000_090A_0B0C";
input_bus1 <= x"001_190A_0B0C";
wait for 10 ns; input_bus <= x"000_0D0E_0F17";
input_bus1 <= x"001_1D0E_0F17";
wait for 10 ns; input_bus <= x"000_0102_0304";
input_bus1 <= x"001_1102_0304";
wait for 10 ns; input_bus <= x"000_0506_0708";
input_bus1 <= x"001_1506_0708";
wait for 10 ns; input_bus <= x"000_090A_0B0C";
input_bus1 <= x"001_190A_0B0C";
wait for 10 ns; input_bus <= x"000_0D0E_0F18";
input_bus1 <= x"001_1D0E_0F18";
wait for 10 ns; input_bus <= x"000_0102_0304";
input_bus1 <= x"001_1102_0304";
wait for 10 ns; input_bus <= x"000_0506_0708";
input_bus1 <= x"001_1506_0708";
wait for 10 ns; input_bus <= x"000_090A_0B0C";
input_bus1 <= x"001_190A_0B0C";
wait for 10 ns; input_bus <= x"000_0D0E_0F19";
input_bus1 <= x"001_1D0E_0F19";
wait for 10 ns; input_bus <= x"000_0102_0304";
input_bus1 <= x"001_1102_0304";
wait for 10 ns; input_bus <= x"000_0506_0708";
input_bus1 <= x"001_1506_0708";
wait for 10 ns; input_bus <= x"000_090A_0B0C";
input_bus1 <= x"001_190A_0B0C";
wait for 10 ns; input_bus <= x"000_0D0E_0F1A";
input_bus1 <= x"001_1D0E_0F1A";
wait for 10 ns; input_bus <= x"000_0102_0304";
input_bus1 <= x"001_1102_0304";
wait for 10 ns; input_bus <= x"000_0506_0708";
input_bus1 <= x"001_1506_0708";
wait for 10 ns; input_bus <= x"000_090A_0B0C";
input_bus1 <= x"001_190A_0B0C";
wait for 10 ns; input_bus <= x"000_0D0E_0F1B";
input_bus1 <= x"001_1D0E_0F1B";
wait for 10 ns; input_bus <= x"000_0102_0304";
input_bus1 <= x"001_1102_0304";
wait for 10 ns; input_bus <= x"000_0506_0708";
input_bus1 <= x"001_1506_0708";
wait for 10 ns; input_bus <= x"000_090A_0B0C";
input_bus1 <= x"001_190A_0B0C";
wait for 10 ns; input_bus <= x"000_0D0E_0F1C";
input_bus1 <= x"001_1D0E_0F1C";
wait for 10 ns; input_bus <= x"000_0102_0304";
input_bus1 <= x"001_1102_0304";
wait for 10 ns; input_bus <= x"000_0506_0708";
input_bus1 <= x"001_1506_0708";
wait for 10 ns; input_bus <= x"000_090A_0B0C";
input_bus1 <= x"001_190A_0B0C";
wait for 10 ns; input_bus <= x"000_0D0E_0F1D";
input_bus1 <= x"001_1D0E_0F1D";
wait for 10 ns; input_bus <= x"000_0102_0304";
input_bus1 <= x"001_1102_0304";
wait for 10 ns; input_bus <= x"000_0506_0708";
input_bus1 <= x"001_1506_0708";
wait for 10 ns; input_bus <= x"000_090A_0B0C";
input_bus1 <= x"001_190A_0B0C";
wait for 10 ns; input_bus <= x"000_0D0E_0F1E";
input_bus1 <= x"001_1D0E_0F1E";
wait for 10 ns; input_bus <= x"000_0102_0304";
input_bus1 <= x"001_1102_0304";
wait for 10 ns; input_bus <= x"000_0506_0708";
input_bus1 <= x"001_1506_0708";
wait for 10 ns; input_bus <= x"000_090A_0B0C";
input_bus1 <= x"001_190A_0B0C";
wait for 10 ns; input_bus <= x"000_0D0E_0F1F";
input_bus1 <= x"001_1D0E_0F1F";
wait for 10 ns; input_bus <= x"000_0000_0001";
input_bus1 <= x"000_0000_0001";
wait for 1000 ns;
end process;


end behavior;