readme.txt

LFSRs as Functional Blocks in Wireless Applications

Readme File
Version 1.0.

Parallel LFSR:
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FPGA Express:
FPGA Express may not infer an SRL16 when the length of the shift register is 2 or less.
Thus a tap on the 1st or 2nd bit will be implemented using two flip flops.  When tap on 
a shift register is immediately after another tap, the tool will use a flip-flop instead 
of creating another SRL16 unless the preserve hierarchy option is checked.

Synplicity:
As in FPGA Express, Synplicity may not infer an SRL16 when the length of the shift 
register is equal or less than 2.

Leonardo Spectrum:
Leonardo Spectrum by default will not merge two SRL16s into a single slice even if they 
share a common input and clock.  In order to get this feature disabled you must set the 
following variable to false:

set virtex_map_srl_pack FALSE

When a tap on a shift register follows immediately after another tap, the tool will 
use a flip-flop instead of creating another SRL16 unless the preserve hierarchy option 
is checked

Implementation:
The map pack option: map -c 1 should be set in order to pack multiple SRL16s into the
same slice.
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Serial LFSR: (VHDL included)

Currently the synthesis tools below cannot infer a dynamically changing output on the 
SRL16E thus the vhdl code attached must instantiate the SRL16E.

An instantiated SRL16E macro also has the advantage of being able to loaded with 
predefined bits at startup.

Synplicity: You must include the Virtex library in order to instantiate any type of 
primitive.