lfsr_ver.v

LFSRs as Functional Blocks in Wireless Applications

//
// Module: 	LFSR_16 
// Design: 	16 bit LFSR using parallel SRL16Es
// Verilog code:	
//
// Simulation	ModelSim EE v5.4c
// Description: 	Inferring SRL16Es to be used in LFSRs
//
//
// Device: 	VIRTEX, VIRTEX-E, Spartan2 Families
//
// Created by: Stephen Lim / XILINX - VIRTEX Applications
// Date: August 2, 2000 -- Version: 1.0
//
// History: 
// 	1. 
//
//   Disclaimer:  THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY 
//                WHATSOEVER AND XILINX SPECIFICALLY DISCLAIMS ANY 
//                IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR
//                A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT.
//
//  Copyright (c) 1999 Xilinx, Inc.  All rights reserved.
/*-----------------------------------------------------------------------------------------------------*/
module LFSR_16 (dout, clk, ce, din, fill);

output [3:0] dout;
input clk;
input ce;
input din;
input fill;

wire tap_u14,tap_u13,tap_u11,tap_u0; 
wire dina;
wire [3:0] dout;

//Instantiating the four inferred SRL16Es below 
SR_16_TAP14  U1 (.dout(tap_u14), .clk(clk), .ce(ce), .din(dina));
SR_16_TAP13  U2 (.dout(tap_u13), .clk(clk), .ce(ce), .din(dina));
SR_16_TAP11  U3 (.dout(tap_u11), .clk(clk), .ce(ce), .din(dina));
SR_16_TAP0   U4 (.dout(tap_u0), .clk(clk), .ce(ce), .din(dina));

assign dout = {tap_u14,tap_u13,tap_u11,tap_u0}; // Output of the LFSR are the four taps.
assign dina = fill?din:!(tap_u14 ^ tap_u13 ^ tap_u11 ^ tap_u0); //XNORing the taps and using this as the MSB shifted input
endmodule

/***************************************************************/
//Inferring a SRL16E element and tapping off after a given number of shifts.  In this case two shifts 
module SR_16_TAP14(dout, clk, ce, din);
output dout;
input clk;
input ce;
input din;

reg [15:0] int;

always @(posedge clk) 
begin
  if (ce)
   int  = {din, int[15:1]};  //Concatenation operation shifts the bits.
end
assign dout = int[14];       //Choosing the select the bit fourteen as the output (2 shifts)

endmodule

/***************************************************************/
//Inferring a SRL16E element and tapping off after a given number of shifts.  In this case three shifts 
module SR_16_TAP13(dout, clk, ce, din);

output dout;
input clk;
input ce;
input din;

reg [15:0] int;

always @(posedge clk) 
begin
  if (ce)
   int  = {din, int[15:1]};
end
assign dout = int[13];

endmodule

/***************************************************************/
//Inferring a SRL16E element and tapping off after a given number of shifts.  In this case five shifts 
module SR_16_TAP11(dout, clk, ce, din);

output dout;
input clk;
input ce;
input din;

reg [15:0] int;

always @(posedge clk) 
begin
  if (ce)
   int  = {din, int[15:1]};
end
assign dout = int[11];

endmodule

/***************************************************************/
//Inferring a SRL16E element and tapping off after a given number of shifts.  In this case sixteen shifts 

module SR_16_TAP0(dout, clk, ce, din);

reg [15:0] int;

output dout;
input clk;
input ce;
input din;

always @(posedge clk) 
begin
  if (ce)
   int  = {din, int[15:1]};
end
assign dout = int[0];

endmodule

/***************************************************************/