lfsr2_ver.v

LFSRs as Functional Blocks in Wireless Applications

//
// Module: 	SRL_16_TAP1
// Design: 	16 bit LFSR using a single instantiated SRL16Es (sequential version)
// Verilog code:	
//
// Simulation	ModelSim EE v5.4c
//
// Description: 	Inferring SRL16Es to be used in LFSRs
//
// Device: 	VIRTEX, VIRTEX-E, Spartan2 Families
//
// Created by: Stephen Lim / XILINX - VIRTEX Applications
// Date: August 2, 2000 -- Version: 1.0
//
// History: 
// 	1. 
//
//   Disclaimer:  THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY 
//                WHATSOEVER AND XILINX SPECIFICALLY DISCLAIMS ANY 
//                IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR
//                A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT.
//
//  Copyright (c) 1999 Xilinx, Inc.  All rights reserved.
/*-----------------------------------------------------------------------------------------------------*/
`include "c:\synplicity\synplify\lib\xilinx\virtex.v"

module SR_16_TAP1 (dout, clk, clk4x, reset, din, fill);

output dout;
input clk;
input clk4x;
input reset;
input din;
input fill;

wire tapd; // Output of SRL16E
wire d;    // Input of DFF
wire q;    // Output of DFF
wire [3:0] addr;  // Dynamically changing address lines

reg [3:0] addr;
reg q;
reg dout;

SRL16E U1 ( .Q(tapd), 
		.A3(addr[3]), 
		.A2(addr[2]), 
		.A1(addr[1]), 
		.A0(addr[0]),
		.D(d),
		.CLK(clk4x),
		.CE(addr[3]));

always @(posedge clk4x or posedge reset) 
begin
  if (reset == 1)
	q <= 1'b1;
  else
   begin
    if (addr[3] == 1'b1)// Because this bit of the address line only changes one out of every four
				// clock cycles, this bit is used to preset the output flip flop.
	q <= 1'b1;
    else
      q <= d;
   end
end

assign d = fill?din:!(q ^ tapd); // Additional logic added so that the user can load in user-defined bits

always @(posedge clk4x or posedge reset)
begin
if (reset == 1)
	addr <= 4'b0001;
else
case (addr)       // Changing the outputs of the shift register to access the correct taps.
    4'b0001 : addr <= 4'b0010;
    4'b0010 : addr <= 4'b0100;
    4'b0100 : addr <= 4'b1111;
    default : addr <= 4'b0001;
endcase  
end

always @(posedge clk or posedge reset) // This process registers the final output at the chip rate clock cycle.  (not required)

begin
if (reset == 1)
	dout <= 1'b0;
else
	dout <= tapd;
end
endmodule