lfsr_vhd.vhd

LFSRs as Functional Blocks in Wireless Applications

--
-- Module: 	LFSR_16 
-- Design: 	16 bit LFSR using parallel SRL16Es
-- VHDL code:	
--
-- Simulation	ModelSim EE v5.4c
--
-- Description: 	Inferring SRL16Es to be used in LFSRs
--
--
-- Device: 	VIRTEX, VIRTEX-E, Spartan2 Families
--
-- Created by: Stephen Lim / XILINX - VIRTEX Applications
-- Date: August 2, 2000 -- Version: 1.0
--
-- History: 
-- 	1. 
--
--   Disclaimer:  THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY 
--                WHATSOEVER AND XILINX SPECIFICALLY DISCLAIMS ANY 
--                IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR
--                A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT.
--
--  Copyright (c) 1999 Xilinx, Inc.  All rights reserved.
-------------------------------------------------------------------------------------------------------

--**********************************************************
--Inferring a SRL16E element and tapping off after a given number of shifts.  In this case two shifts.
library IEEE;
use IEEE.std_logic_1164.all;

entity SR_16_TAP14 is
    port (
        CLK: in STD_LOGIC;
        CE: in STD_LOGIC;
        DIN: in STD_LOGIC;
        DOUT: out STD_LOGIC
    );
end SR_16_TAP14;

architecture SR_16_TAP14_arch of SR_16_TAP14 is

signal REG: STD_LOGIC_VECTOR(15 downto 0);

begin
  
process (CLK)
begin

   if CLK'event and CLK='1' then
   	if CE = '1' then
   	REG <= DIN & REG(15 downto 1);  --Concatenation operation shifts the bits.
   	end if;
   end if;
 DOUT <= REG(14);				  --Choosing the select the bit fourteen as the output (2 shifts)
end process;

end SR_16_TAP14_arch;

--**********************************************************
--Inferring a SRL16E element and tapping off after a given number of shifts.  In this case three shifts.
library IEEE;
use IEEE.std_logic_1164.all;

entity SR_16_TAP13 is
    port (
        CLK: in STD_LOGIC;
        CE: in STD_LOGIC;
        DIN: in STD_LOGIC;
        DOUT: out STD_LOGIC
    );
end SR_16_TAP13;

architecture SR_16_TAP13_arch of SR_16_TAP13 is

signal REG: STD_LOGIC_VECTOR(15 downto 0);

begin
  
process (CLK)
begin

   if CLK'event and CLK='1' then
   	if CE = '1' then
   	REG <= DIN & REG(15 downto 1);
   	end if;
   end if;
 DOUT <= REG(13);
end process;
  
end SR_16_TAP13_arch;

--**********************************************************
--Inferring a SRL16E element and tapping off after a given number of shifts.  In this case five shifts.
library IEEE;
use IEEE.std_logic_1164.all;

entity SR_16_TAP11 is
    port (
        CLK: in STD_LOGIC;
        CE: in STD_LOGIC;
        DIN: in STD_LOGIC;
        DOUT: out STD_LOGIC
    );
end SR_16_TAP11;

architecture SR_16_TAP11_arch of SR_16_TAP11 is

signal REG: STD_LOGIC_VECTOR(15 downto 0);

begin
  
process (CLK)
begin

   if CLK'event and CLK='1' then
   	if CE = '1' then
   	REG <= DIN & REG(15 downto 1);
   	end if;
   end if;
 DOUT <= REG(11);
end process;
  
end SR_16_TAP11_arch;

--***************************************************************************
--Inferring a SRL16E element and tapping off after a given number of shifts.  In this case sixteen shifts.

library IEEE;
use IEEE.std_logic_1164.all;

entity SR_16_TAP0 is
    port (
        CLK: in STD_LOGIC;
        CE: in STD_LOGIC;
        DIN: in STD_LOGIC;
        DOUT: out STD_LOGIC
    );
end SR_16_TAP0;

architecture SR_16_TAP0_arch of SR_16_TAP0 is

signal REG: STD_LOGIC_VECTOR(15 downto 0);

begin

process (CLK)
begin

   if CLK'event and CLK='1' then
   	if CE = '1' then
   	REG <= DIN & REG(15 downto 1);
   	end if;
   end if;
 DOUT <= REG(0);
end process;

end SR_16_TAP0_arch;
--**************************************************************************

library IEEE;
use IEEE.std_logic_1164.all;

entity LFSR_16 is
    port (
        CLK: in STD_LOGIC;
        CE: in STD_LOGIC;
        DIN: in STD_LOGIC;
        FILL: in STD_LOGIC;
        DOUT: out STD_LOGIC_VECTOR(3 downto 0)
    );
end LFSR_16;

architecture LFSR_16_arch of LFSR_16 is

signal DINA: STD_LOGIC;
signal TAP_U14: STD_LOGIC;
signal TAP_U13: STD_LOGIC;
signal TAP_U11: STD_LOGIC;
signal TAP_U0: STD_LOGIC;

--Instantiating and declaring the four inferred SRL16Es above
component SR_16_TAP14 port(
	CLK, DIN, CE: in STD_LOGIC;
	DOUT: out STD_LOGIC);
end component;

component SR_16_TAP13 port(
	CLK, DIN,CE: in STD_LOGIC;
	DOUT: out STD_LOGIC);
end component;

component SR_16_TAP11 port(
	CLK, DIN,CE: in STD_LOGIC;
	DOUT: out STD_LOGIC);
end component;

component SR_16_TAP0 port(
	CLK, DIN,CE: in STD_LOGIC;
	DOUT: out STD_LOGIC);
end component;

begin

U1: SR_16_TAP14  port map (CLK => CLK, CE => CE, DIN => DINA, DOUT => TAP_U14);
U2: SR_16_TAP13  port map (CLK => CLK, CE => CE, DIN => DINA, DOUT => TAP_U13);
U3: SR_16_TAP11  port map (CLK => CLK, CE => CE, DIN => DINA, DOUT => TAP_U11);
U4: SR_16_TAP0 port map (CLK => CLK, CE => CE, DIN => DINA, DOUT => TAP_U0);

DOUT <= TAP_U14 & TAP_U13 & TAP_U11 & TAP_U0; -- Output of the LFSR are the four taps.

process (DIN, FILL,TAP_U14,TAP_U13,TAP_U11,TAP_U0)
begin

	if FILL = '1' then --Added logic to shift in User defined bits.
		DINA <= DIN;
	else
		DINA <= not(TAP_U14 xor TAP_U13 xor TAP_U11 xor TAP_U0); -- XNORing the taps and using this as the MSB shifted input.
	end if;
end process;
end LFSR_16_arch;