readme.txt

来自「Gold Code Generators in Virtex Devices」· 文本 代码 · 共 47 行

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-       Readme for VHDL and Verilog source code         -
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The design was targeted to a V50-6BG256 device.
Exemplar Spectrum, Synplicity Synplify and Synopsys
FPGA Express all synthesize this code properly.


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- VHDL							-
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Files Hierarchy:
	vhd_top.vhd (Top-level)
	vhd_suba.vhd (Implementation of one LFSR)
	vhd_subb.vhd (Implementation of second LFSR)

Notes:
	- The sequence length can be configured by 
	  modifiying the "generic" parameters listed
	  in the entity statements for vhd_suba.vhd and
	  vhd_subb.vhd files
	- The CLKDLL component is not inserted into the
	  code. To see how to use the CLKDLL in VHDL
	  see solution 5649 at http://support.xilinx.com
	
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- Verilog							-
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Files Hierarchy:
	infer.v (Top-level)
	sub_a.v (Implementation of one LFSR)
	sub_b.v (Implementation of second LFSR)

Notes:
	- The sequence length can be configured by 
	  modifiying the parameters listed after the
	  module declaration in the sub_a.v and sub_b.v
	  files.
  	- The CLKDLL component is not inserted into the
	  code. To see how to use the CLKDLL in VHDL
	  see solution 5649 at http://support.xilinx.com