tb_cam_ramb4.v

Using Block RAM for High-Performance Read.Write Cams

`timescale 1 ns/100 ps

`include "parameters.v"

module TB_CAM_RAMB4();

reg [7:0] DATA_IN;
reg [3:0] ADDR;
reg WRITE_ENABLE;
reg ERASE_WRITE;
reg WRITE_RAM;
reg CLK;
reg MATCH_ENABLE;
reg MATCH_RST;
wire [15:0] MATCH;


// CAM_RAMB4 instantiation

CAM_RAMB4 UUT (.DATA_IN(DATA_IN), .ADDR(ADDR), .WRITE_ENABLE(WRITE_ENABLE),
               .ERASE_WRITE(ERASE_WRITE), .WRITE_RAM(WRITE_RAM), .CLK(CLK),
               .MATCH_ENABLE(MATCH_ENABLE), .MATCH_RST(MATCH_RST), .MATCH(MATCH));
               
// Clock Generation

initial
  CLK = 1'b0;
               
always
  #(`clock_period/2) CLK = ~CLK;
  
  
// Defining Stimulus

initial
 begin
 
  DATA_IN = 8'h00;
  ADDR = 4'h0;
  WRITE_ENABLE = 1'b0;
  ERASE_WRITE = 1'b0;
  WRITE_RAM = 1'b0;
  MATCH_ENABLE = 1'b0;
  MATCH_RST = 1'b1;
  //MATCH = 16'hXXXX;    // Expected value of the output
  
  delay_1_clock;
  
  // Synchronous Reset
  DATA_IN = 8'h00;
  ADDR = 4'h0;
  WRITE_ENABLE = 1'b0;
  ERASE_WRITE = 1'b0;
  WRITE_RAM = 1'b0;
  MATCH_ENABLE = 1'b1;
  MATCH_RST = 1'b0;
  //MATCH = 16'h0000;    // Expected value of the output
  
  delay_1_clock;
  
  // 1-Write Operation DATA_IN at the address ADDR
  DATA_IN = 8'h01;
  ADDR = 4'h2;
  WRITE_ENABLE = 1'b1;
  ERASE_WRITE = 1'b0;
  WRITE_RAM = 1'b1;
  MATCH_ENABLE = 1'b0;
  MATCH_RST = 1'b1;
  //MATCH = 16'h0000;    // Expected value of the output
  
  delay_1_clock;
  
  DATA_IN = 8'h00;
  ADDR = 4'h2;
  WRITE_ENABLE = 1'b1;
  ERASE_WRITE = 1'b1;
  WRITE_RAM = 1'b0;
  MATCH_ENABLE = 1'b0;
  MATCH_RST = 1'b1;
  //MATCH = 16'h0000;    // Expected value of the output
  
  delay_1_clock;
  
  // Dummy clock cycle
  DATA_IN = 8'h00;
  ADDR = 4'h0;
  WRITE_ENABLE = 1'b0;
  ERASE_WRITE = 1'b0;
  WRITE_RAM = 1'b0;
  MATCH_ENABLE = 1'b0;
  MATCH_RST = 1'b1;
  //MATCH = 16'h0000;    // Expected value of the output
  
  delay_1_clock;
  
  // 1-Read Operation of the first data
  DATA_IN = 8'h01;
  ADDR = 4'h0;
  WRITE_ENABLE = 1'b0;
  ERASE_WRITE = 1'b0;
  WRITE_RAM = 1'b0;
  MATCH_ENABLE = 1'b1;
  MATCH_RST = 1'b1;
  //MATCH = 16'h0004;    // Expected value of the output
  
  delay_1_clock;
  
  DATA_IN = 8'h00;
  ADDR = 4'h0;
  WRITE_ENABLE = 1'b0;
  ERASE_WRITE = 1'b0;
  WRITE_RAM = 1'b0;
  MATCH_ENABLE = 1'b0;
  MATCH_RST = 1'b1;
  //MATCH = 16'h0004;    // Expected value of the output
  
  delay_1_clock;
  
  // 2-Write Operation DATA_IN at the address ADDR
  DATA_IN = 8'hDF;
  ADDR = 4'hC;
  WRITE_ENABLE = 1'b1;
  ERASE_WRITE = 1'b0;
  WRITE_RAM = 1'b1;
  MATCH_ENABLE = 1'b1;
  MATCH_RST = 1'b1;
  //MATCH = 16'h0000;    // Expected value of the output
  
  delay_1_clock;
  
  DATA_IN = 8'hDF;
  ADDR = 4'hC;
  WRITE_ENABLE = 1'b1;
  ERASE_WRITE = 1'b1;
  WRITE_RAM = 1'b0;
  MATCH_ENABLE = 1'b0;
  MATCH_RST = 1'b1;
  //MATCH = 16'h0000;    // Expected value of the output
  
  delay_1_clock;
  
  // 3-Write Operation DATA_IN at the address ADDR
  DATA_IN = 8'hA0;
  ADDR = 4'hF;
  WRITE_ENABLE = 1'b1;
  ERASE_WRITE = 1'b0;
  WRITE_RAM = 1'b1;
  MATCH_ENABLE = 1'b0;
  MATCH_RST = 1'b1;
  //MATCH = 16'h0000;    // Expected value of the output
  
  delay_1_clock;
  
  DATA_IN = 8'hA0;
  ADDR = 4'hF;
  WRITE_ENABLE = 1'b1;
  ERASE_WRITE = 1'b1;
  WRITE_RAM = 1'b0;
  MATCH_ENABLE = 1'b0;
  MATCH_RST = 1'b1;
  //MATCH = 16'h0000;    // Expected value of the output
  
  delay_1_clock;
  
  // 4-Write Operation DATA_IN at the address ADDR
  DATA_IN = 8'h69;
  ADDR = 4'h5;
  WRITE_ENABLE = 1'b1;
  ERASE_WRITE = 1'b0;
  WRITE_RAM = 1'b1;
  MATCH_ENABLE = 1'b0;
  MATCH_RST = 1'b1;
  //MATCH = 16'h0000;    // Expected value of the output
  
  delay_1_clock;
  
  DATA_IN = 8'h00;
  ADDR = 4'h5;
  WRITE_ENABLE = 1'b1;
  ERASE_WRITE = 1'b1;
  WRITE_RAM = 1'b0;
  MATCH_ENABLE = 1'b0;
  MATCH_RST = 1'b1;
  //MATCH = 16'h0000;    // Expected value of the output
  
  delay_1_clock;
  
  // 4 & 3 & 2 & non-existing data & 1 read back
  DATA_IN = 8'h69;
  ADDR = 4'h0;
  WRITE_ENABLE = 1'b0;
  ERASE_WRITE = 1'b0;
  WRITE_RAM = 1'b0;
  MATCH_ENABLE = 1'b1;
  MATCH_RST = 1'b1;
  //MATCH = 16'h0020;    // Expected value of the output
  
  delay_1_clock;
  
  DATA_IN = 8'hA0;
  ADDR = 4'h0;
  WRITE_ENABLE = 1'b0;
  ERASE_WRITE = 1'b0;
  WRITE_RAM = 1'b0;
  MATCH_ENABLE = 1'b1;
  MATCH_RST = 1'b1;
  //MATCH = 16'h8000;    // Expected value of the output
  
  delay_1_clock;
  
  DATA_IN = 8'hDF;
  ADDR = 4'h0;
  WRITE_ENABLE = 1'b0;
  ERASE_WRITE = 1'b0;
  WRITE_RAM = 1'b0;
  MATCH_ENABLE = 1'b1;
  MATCH_RST = 1'b1;
  //MATCH = 16'h1000;    // Expected value of the output
  
  delay_1_clock;
  
  DATA_IN = 8'h61;
  ADDR = 4'h0;
  WRITE_ENABLE = 1'b0;
  ERASE_WRITE = 1'b0;
  WRITE_RAM = 1'b0;
  MATCH_ENABLE = 1'b1;
  MATCH_RST = 1'b1;
  //MATCH = 16'h0000;    // Expected value of the output
  
  delay_1_clock;
  
  DATA_IN = 8'h01;
  ADDR = 4'h0;
  WRITE_ENABLE = 1'b0;
  ERASE_WRITE = 1'b0;
  WRITE_RAM = 1'b0;
  MATCH_ENABLE = 1'b1;
  MATCH_RST = 1'b1;
  //MATCH = 16'h0004;    // Expected value of the output
  
  delay_1_clock;
  
  // 5-Write Operation DATA_IN at the address ADDR (same as the first address)
  DATA_IN = 8'hFF;
  ADDR = 4'h2;
  WRITE_ENABLE = 1'b1;
  ERASE_WRITE = 1'b0;
  WRITE_RAM = 1'b1;
  MATCH_ENABLE = 1'b0;
  MATCH_RST = 1'b1;
  //MATCH = 16'h0004;    // Expected value of the output
  
  delay_1_clock;
  
  DATA_IN = 8'hFF;
  ADDR = 4'h2;
  WRITE_ENABLE = 1'b1;
  ERASE_WRITE = 1'b1;
  WRITE_RAM = 1'b0;
  MATCH_ENABLE = 1'b0;
  MATCH_RST = 1'b1;
  //MATCH = 16'h0004;    // Expected value of the output
  
  delay_1_clock;
  
  // 1 read back then erase n 1
  DATA_IN = 8'h01;
  ADDR = 4'h0;
  WRITE_ENABLE = 1'b0;
  ERASE_WRITE = 1'b0;
  WRITE_RAM = 1'b0;
  MATCH_ENABLE = 1'b1;
  MATCH_RST = 1'b1;
  //MATCH = 16'h0000;    // Expected value of the output
  
  delay_1_clock;
  
  // 6-Write Operation DATA_IN (same as n 1) at the address ADDR
  DATA_IN = 8'h01;
  ADDR = 4'h3;
  WRITE_ENABLE = 1'b1;
  ERASE_WRITE = 1'b0;
  WRITE_RAM = 1'b1;
  MATCH_ENABLE = 1'b0;
  MATCH_RST = 1'b1;
  //MATCH = 16'h0000;    // Expected value of the output
  
  delay_1_clock;
  
  DATA_IN = 8'h01;
  ADDR = 4'h3;
  WRITE_ENABLE = 1'b1;
  ERASE_WRITE = 1'b1;
  WRITE_RAM = 1'b0;
  MATCH_ENABLE = 1'b0;
  MATCH_RST = 1'b1;
  //MATCH = 16'h0000;    // Expected value of the output
  
  delay_1_clock;
  
  // 5 & 6 & non-existing data read back
  DATA_IN = 8'hFF;
  ADDR = 4'h0;
  WRITE_ENABLE = 1'b0;
  ERASE_WRITE = 1'b0;
  WRITE_RAM = 1'b0;
  MATCH_ENABLE = 1'b1;
  MATCH_RST = 1'b1;
  //MATCH = 16'h0004;    // Expected value of the output
  
  delay_1_clock;
  
  DATA_IN = 8'h81;
  ADDR = 4'h0;
  WRITE_ENABLE = 1'b0;
  ERASE_WRITE = 1'b0;
  WRITE_RAM = 1'b0;
  MATCH_ENABLE = 1'b1;
  MATCH_RST = 1'b1;
  //MATCH = 16'h0000;    // Expected value of the output
  
  delay_1_clock;
  
  DATA_IN = 8'h01;
  ADDR = 4'h0;
  WRITE_ENABLE = 1'b0;
  ERASE_WRITE = 1'b0;
  WRITE_RAM = 1'b0;
  MATCH_ENABLE = 1'b1;
  MATCH_RST = 1'b1;
  //MATCH = 16'h0008;    // Expected value of the output
  
  delay_1_clock;
  
  // Dummy clock cycle/Test Match Reset
  DATA_IN = 8'h00;
  ADDR = 4'h0;
  WRITE_ENABLE = 1'b0;
  ERASE_WRITE = 1'b0;
  WRITE_RAM = 1'b0;
  MATCH_ENABLE = 1'b1;
  MATCH_RST = 1'b0;
  //MATCH = 16'h0000;    // Expected value of the output
  
  delay_1_clock;
  
  // 7-Write Operation DATA_IN at the address ADDR "0000"
  DATA_IN = 8'h01;
  ADDR = 4'h0;
  WRITE_ENABLE = 1'b1;
  ERASE_WRITE = 1'b0;
  WRITE_RAM = 1'b1;
  MATCH_ENABLE = 1'b0;
  MATCH_RST = 1'b1;
  //MATCH = 16'h0000;    // Expected value of the output
  
  delay_1_clock;
  
  DATA_IN = 8'h01;
  ADDR = 4'h0;
  WRITE_ENABLE = 1'b1;
  ERASE_WRITE = 1'b1;
  WRITE_RAM = 1'b0;
  MATCH_ENABLE = 1'b0;
  MATCH_RST = 1'b1;
  //MATCH = 16'h0000;    // Expected value of the output
  
  delay_1_clock;
  
  // 8-Write Operation DATA_IN (same as n 4) at the address ADDR
  DATA_IN = 8'hC2;
  ADDR = 4'h5;
  WRITE_ENABLE = 1'b1;
  ERASE_WRITE = 1'b0;
  WRITE_RAM = 1'b1;
  MATCH_ENABLE = 1'b0;
  MATCH_RST = 1'b1;
  //MATCH = 16'h0000;    // Expected value of the output
  
  delay_1_clock;
  
  DATA_IN = 8'hC2;
  ADDR = 4'h5;
  WRITE_ENABLE = 1'b1;
  ERASE_WRITE = 1'b1;
  WRITE_RAM = 1'b0;
  MATCH_ENABLE = 1'b0;
  MATCH_RST = 1'b1;
  //MATCH = 16'h0000;    // Expected value of the output
  
  delay_1_clock;
  
  // Multi-matched ( n 6 & n 7) & 8 & 5 read back
  DATA_IN = 8'h01;
  ADDR = 4'h0;
  WRITE_ENABLE = 1'b0;
  ERASE_WRITE = 1'b0;
  WRITE_RAM = 1'b0;
  MATCH_ENABLE = 1'b1;
  MATCH_RST = 1'b1;
  //MATCH = 16'h0009;    // Expected value of the output
  
  delay_1_clock;
  
  DATA_IN = 8'hC2;
  ADDR = 4'h0;
  WRITE_ENABLE = 1'b0;
  ERASE_WRITE = 1'b0;
  WRITE_RAM = 1'b0;
  MATCH_ENABLE = 1'b1;
  MATCH_RST = 1'b1;
  //MATCH = 16'h0020;    // Expected value of the output
  
  delay_1_clock;
  
  DATA_IN = 8'hFF;
  ADDR = 4'h0;
  WRITE_ENABLE = 1'b0;
  ERASE_WRITE = 1'b0;
  WRITE_RAM = 1'b0;
  MATCH_ENABLE = 1'b1;
  MATCH_RST = 1'b1;
  //MATCH = 16'h0004;    // Expected value of the output
  
  delay_1_clock;
  
  // Dummy Clock cycles
  DATA_IN = 8'h00;
  ADDR = 4'h0;
  WRITE_ENABLE = 1'b0;
  ERASE_WRITE = 1'b0;
  WRITE_RAM = 1'b0;
  MATCH_ENABLE = 1'b0;
  MATCH_RST = 1'b1;
  //MATCH = 16'h0004;    // Expected value of the output
  
  delay_1_clock;
  
  //9-Write Operation DATA_IN (same as n4 & n8) at the address ADDR
  DATA_IN = 8'hC2;
  ADDR = 4'hC;
  WRITE_ENABLE = 1'b1;
  ERASE_WRITE = 1'b0;
  WRITE_RAM = 1'b1;
  MATCH_ENABLE = 1'b0;
  MATCH_RST = 1'b1;
  //MATCH = 16'h0004;    // Expected value of the output
  
  delay_1_clock;
  
  DATA_IN = 8'hC2;
  ADDR = 4'hC;
  WRITE_ENABLE = 1'b1;
  ERASE_WRITE = 1'b1;
  WRITE_RAM = 1'b0;
  MATCH_ENABLE = 1'b0;
  MATCH_RST = 1'b1;
  //MATCH = 16'h0004;    // Expected value of the output
  
  delay_1_clock;
  
  // 10-Write Operation DATA_IN (same as n4 & n8) at the address ADDR 
  DATA_IN = 8'hC2;
  ADDR = 4'h7;
  WRITE_ENABLE = 1'b1;
  ERASE_WRITE = 1'b0;
  WRITE_RAM = 1'b1;
  MATCH_ENABLE = 1'b0;
  MATCH_RST = 1'b1;
  //MATCH = 16'h0004;    // Expected value of the output
  
  delay_1_clcok;
  
  DATA_IN = 8'hC2;
  ADDR = 4'h7;
  WRITE_ENABLE = 1'b1;
  ERASE_WRITE = 1'b1;
  WRITE_RAM = 1'b0;
  MATCH_ENABLE = 1'b0;
  MATCH_RST = 1'b1;
  //MATCH = 16'h0004;    // Expected value of the output
  
  delay_1_clock;
  
  // Read Multi-matches (n 8 & n 9 & n 10) read back
  DATA_IN = 8'h01;
  ADDR = 4'h0;
  WRITE_ENABLE = 1'b0;
  ERASE_WRITE = 1'b0;
  WRITE_RAM = 1'b0;
  MATCH_ENABLE = 1'b1;
  MATCH_RST = 1'b1;
  //MATCH = 16'h0009;    // Expected value of the output
  
  delay_1_clock;
  
  DATA_IN = 8'hC2;
  ADDR = 4'h0;
  WRITE_ENABLE = 1'b0;
  ERASE_WRITE = 1'b0;
  WRITE_RAM = 1'b0;
  MATCH_ENABLE = 1'b1;
  MATCH_RST = 1'b1;
  //MATCH = 16'h10A0;    // Expected value of the output
  
  delay_1_clock;
  
  // Synchronous Reset
  DATA_IN = 8'h00;
  ADDR = 4'h0;
  WRITE_ENABLE = 1'b0;
  ERASE_WRITE = 1'b0;
  WRITE_RAM = 1'b0;
  MATCH_ENABLE = 1'b1;
  MATCH_RST = 1'b0;
  //MATCH = 16'h0000;    // Expected value of the output
  
  delay_1_clock;
  
  // Dummy Clcok cycle
  DATA_IN = 8'h00;
  ADDR = 4'h0;
  WRITE_ENABLE = 1'b0;
  ERASE_WRITE = 1'b0;
  WRITE_RAM = 1'b0;
  MATCH_ENABLE = 1'b0;
  MATCH_RST = 1'b1;
  //MATCH = 16'h0000;    // Expected value of the output
  
  delay_1_clock;
  
  DATA_IN = 8'h00;
  ADDR = 4'h0;
  WRITE_ENABLE = 1'b0;
  ERASE_WRITE = 1'b0;
  WRITE_RAM = 1'b0;
  MATCH_ENABLE = 1'b0;
  MATCH_RST = 1'b1;
  //MATCH = 16'h0000;    // Expected value of the output
  
  end // initial for Defining Stimulus
  
  task delay_1_clock;
     begin
       #1;
       @ (posedge CLK);
       #6;
     end
  endtask  // delay_1_clock
  
  endmodule // TB_CAM_RAMB4