📄 cam_generic_8s.v
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//
// Module: CAM_generic_8s
// Design: CAM_Top
// Verilog code: Hierarchical RTL
// Instantiate CAM_RAMB4
// Instantiate INIT_RAMB4_S1_S16
// Instantiate INIT_8_RAM16x1s
// Instantiate ENCODE_4_LSB
// Instantiate DECODE_X
// Instantiate ENCODE_X_MSB
// Choice the right ENCODE and DECODE modules according to the number of CAM16x8s
// If "nb_cam16x8s" = 2 then ENCODE_1_MSB and DECODE_1 must be used: 1 bit to decode 2 CAM16x8s
// If "nb_cam16x8s" = 4 then ENCODE_2_MSB and DECODE_2 must be used: 2 bits to decode 4 CAM16x8s
// If "nb_cam16x8s" = 8 then ENCODE_3_MSB and DECODE_3 must be used: 3 bits to decode 8 CAM16x8s
// If "nb_cam16x8s" = 16 then ENCODE_4_MSB and DECODE_4 must be used: 4 bits to decode 16 CAM16x8s
// Note: Configuration is not supported by synthesis tools
//
//
// Description: Instantiate "nb_cam16x8s" CAM_RAMB4 (see generic)
// "nb_cam16x8s" x 16 words depth x 8 bits width
// 1 clock cycle Read (or Match),
// 2 clock cycles Write (Erase on the first clock then Store on the second) / If only 1 clock cycle => Erase Only.
// MATCH_OK indicates one or more matches is/are found.
// MATCH_ADDR ouput the address of the match, if ONLY ONE is found
// ADDR_VALID indicates when MATCH_ADDR is a valid address (Optional)
//
// Device: VIRTEX Family (VIRTEX & VIRTEX-E)
// modules CAM_RAMB4 fits in 1 BlockRAM column (+ CLB)
// If "nb_cam16x8s" = 4 then CAM64x8s (fits in 1 XCV50 or XCV50E BlockRam Column)
// If "nb_cam16x8s" = 8 then CAM128x8s (fits in 1 XCV300 or XCV300E BlockRam Column)
// If "nb_cam16x8s" = 16 then CAM256x8s (fits in 1 XCV1000 or XCV1000E BlockRam Column)
//
// Synthesis_tool Synopsys FPGA Express ver. 3.3
// Enable Synthesis Option: Verilog Pre-procesor
//
//
//
// Created by: Jean-Louis BRELET / XILINX - VIRTEX Applications
// Converted to Verilog: Maria George - VIRTEX Applications
// Date: December 8, 1999
// Version: 1.0
//
// History:
// 1. 12/08/99 MG - Translated to Verilog
//
// Disclaimer: THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY
// WHATSOEVER AND XILINX SPECIFICALLY DISCLAIMS ANY
// IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR
// A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT.
//
// Copyright (c) 1999 Xilinx, Inc. All rights reserved.
//////////////////////////////////////////////////////////////////////////////////////////////////////-
`include "parameters.v"
module CAM_generic_8s (DATA_IN, // Data to compare or to write
ADDR, // Address only when write
WRITE_ENABLE, // Write Enable if high (2 clock cycles)
CLK,
MATCH_ENABLE, //Enable to find a match,else No change on Match Bus
MATCH_RST, //Synchronous.If'0'MATCH bus is zero,when MATCH_ENABLE=1
GLOBAL_RST, //Global Asynchronous FF Reset
R_MATCH_ADDR, //Registered Match address found
`ifdef use_addr_valid
ADDR_VALID, //Double the size of the encoder.Need only if simultaneous matches can occur
`endif
R_MATCH_OK // '1' if MATCH found. Registered
);
input CLK, WRITE_ENABLE, MATCH_ENABLE, MATCH_RST, GLOBAL_RST;
input [7:0] DATA_IN;
input [`addr_width-1:0] ADDR;
output [`addr_width-1:0] R_MATCH_ADDR;
output R_MATCH_OK;
`ifdef use_addr_valid
output ADDR_VALID;
`endif
reg [`addr_width-1:0] R_MATCH_ADDR;
reg R_MATCH_OK;
`ifdef use_addr_valid
reg ADDR_VALID;
`endif
// Internal Signal Declarations
wire ERASE_WRITE; // Erase then Write Enable (2 clock cycles)
reg WRITE_RAM; // Write enable in the RAM16x1s
wire [`nb_cam16x8s-1:0] BUS_WRITE_ENABLE; // Decode the CAM16x1s to be addressed
`ifdef use_addr_valid
wire [`addr_width-1:0] BUS_ADDR_VALID; // Optional
`endif
wire [`nb_cam16x8s-1:0] BUS_MATCH_OK;
wire [`addr_width-1:0] MATCH_ADDR; // Match address found
wire MATCH_OK; // '1' if MATCH found
wire [15:0] MATCH_ARRAY_0, MATCH_ARRAY_1;
//If nb_cam16x8s = 16 then 16 MATCH_ARRAY and ADDR_ARRAY signals need to be declared.
//wire [15:0] MATCH_ARRAY_0, MATCH_ARRAY_1,MATCH_ARRAY_2,MATCH_ARRAY_3,MATCH_ARRAY_4,MATCH_ARRAY_5,MATCH_ARRAY_6,MATCH_ARRAY_7,
// MATCH_ARRAY_8,MATCH_ARRAY_9,MATCH_ARRAY_10,MATCH_ARRAY_11,MATCH_ARRAY_12,MATCH_ARRAY_13,MATCH_ARRAY_14,MATCH_ARRAY_15;
//wire [15:0] ADDR_ARRAY_0, ADDR_ARRAY_1,ADDR_ARRAY_2,ADDR_ARRAY_3,ADDR_ARRAY_4,ADDR_ARRAY_5,ADDR_ARRAY_6,ADDR_ARRAY_7,
// ADDR_ARRAY_8,ADDR_ARRAY_9,ADDR_ARRAY_10,ADDR_ARRAY_11,ADDR_ARRAY_12,ADDR_ARRAY_13,ADDR_ARRAY_14,ADDR_ARRAY_15;
wire [3:0] ADDR_ARRAY_0, ADDR_ARRAY_1;
// In the "Write Enable" mode, the first clock cycle erases the data, then in the 2nd clock cycle the new data is written.
// A 1 clock cycle WRITE_ENABLE erases only the data.
// RAM16x1s are read to erase the RAMB4 ONLY, used to find a match.
// Does not care if the data is not erased in the RAM16x1s
// Generate a Write Enable for the RAM16x1s
// CYCLE_ERASE
always @ (posedge CLK or posedge GLOBAL_RST)
begin
if (GLOBAL_RST)
WRITE_RAM = 1'b0;
else if (WRITE_ENABLE == 1'b0)
WRITE_RAM = 1'b0;
else
WRITE_RAM = !(WRITE_RAM);
end // CYCLE_ERASE
// Generate an Erase signal '0' then a Write signal '1' for the RAMB4
// If WRITE_ENABLE is deasserted after 1 clock cycle, the WRITE is not valid (WRITE_ENABLE is used for WEA port)
assign ERASE_WRITE = !(WRITE_RAM);
//Create the Write Enable signal for each CAM_RAMB4 = CAM 32 words
DECODE_1 DECODE_X (.ADDR(ADDR[`addr_width-1:4]), .ENABLE(WRITE_ENABLE), .BINARY_ADDR(BUS_WRITE_ENABLE));
//Create the write enable signal for each CAM_RAMB4 = CAM 64 words
//DECODE_2 DECODE_X (.ADDR(ADDR[`addr_width-1:4]), .ENABLE(WRITE_ENABLE), .BINARY_ADDR(BUS_WRITE_ENABLE));
//Create the write enable signal for each CAM_RAMB4 = CAM 128 words
//DECODE_3 DECODE_X (.ADDR(ADDR[`addr_width-1:4]), .ENABLE(WRITE_ENABLE), .BINARY_ADDR(BUS_WRITE_ENABLE));
//Create the write enable signal for each CAM_RAMB4 = CAM 256 words
//DECODE_4 DECODE_X (.ADDR(ADDR[`addr_width-1:4]), .ENABLE(WRITE_ENABLE), .BINARY_ADDR(BUS_WRITE_ENABLE));
//CAM_RAMB4 and ENCODE_X_LSB instantiation. These have to be instantiated as many times as nb_cam16x8s.
//In this case it is 2, therefore just 2 instantiations.
CAM_RAMB4 CAM_X_RAMB4_0 (.DATA_IN(DATA_IN[7:0]), .ADDR(ADDR[3:0]), .WRITE_ENABLE(BUS_WRITE_ENABLE[0]),
.ERASE_WRITE(ERASE_WRITE), .WRITE_RAM(WRITE_RAM), .CLK(CLK), .MATCH_ENABLE(MATCH_ENABLE),
.MATCH_RST(MATCH_RST), .MATCH(MATCH_ARRAY_0));
// Generate the Match Address
ENCODE_4_LSB ENCODE_X_LSB_0 (.BINARY_ADDR(MATCH_ARRAY_0),
.MATCH_ADDR(ADDR_ARRAY_0),
`ifdef use_addr_valid
.ADDR_VALID(BUS_ADDR_VALID[0]),
`endif
.MATCH_OK(BUS_MATCH_OK[0]));
CAM_RAMB4 CAM_X_RAMB4_1 (.DATA_IN(DATA_IN[7:0]), .ADDR(ADDR[3:0]), .WRITE_ENABLE(BUS_WRITE_ENABLE[1]),
.ERASE_WRITE(ERASE_WRITE), .WRITE_RAM(WRITE_RAM), .CLK(CLK), .MATCH_ENABLE(MATCH_ENABLE),
.MATCH_RST(MATCH_RST), .MATCH(MATCH_ARRAY_1));
// Generate the Match Address
ENCODE_4_LSB ENCODE_X_LSB_1 (.BINARY_ADDR(MATCH_ARRAY_1),
.MATCH_ADDR(ADDR_ARRAY_1),
`ifdef use_addr_valid
.ADDR_VALID(BUS_ADDR_VALID[1]),
`endif
.MATCH_OK(BUS_MATCH_OK[1]));
//If the value of nb_cam16x8s = 16, then 16 instantiations required.
//CAM_RAMB4 CAM_X_RAMB4_2 (.DATA_IN(DATA_IN[7:0]), .ADDR(ADDR[3:0]), WRITE_ENABLE(BUS_WRITE_ENABLE[2]),
// .ERASE_WRITE(ERASE_WRITE), .WRITE_RAM(WRITE_RAM), .CLK(CLK), .MATCH_ENABLE(MATCH_ENABLE),
// .MATCH_RST(MATCH_RST), .MATCH(MATCH_ARRAY_2));
// Generate the Match Address
//ENCODE_4_LSB ENCODE_X_LSB_2 (.BINARY_ADDR(MATCH_ARRAY_2), .MATCH_ADDR(ADDR_ARRAY_2),
// `ifdef use_addr_valid
// .ADDR_VALID(BUS_ADDR_VALID[2]),
// `endif
// .MATCH_OK(BUS_MATCH_OK[2]));
//CAM_RAMB4 CAM_X_RAMB4_3 (.DATA_IN(DATA_IN[7:0]), .ADDR(ADDR[3:0]), WRITE_ENABLE(BUS_WRITE_ENABLE[3]),
// .ERASE_WRITE(ERASE_WRITE), .WRITE_RAM(WRITE_RAM), .CLK(CLK), .MATCH_ENABLE(MATCH_ENABLE),
// .MATCH_RST(MATCH_RST), .MATCH(MATCH_ARRAY_3));
// Generate the Match Address
//ENCODE_4_LSB ENCODE_X_LSB_3 (.BINARY_ADDR(MATCH_ARRAY_3), .MATCH_ADDR(ADDR_ARRAY_3),
// `ifdef use_addr_valid
// .ADDR_VALID(BUS_ADDR_VALID[3]),
// `endif
// .MATCH_OK(BUS_MATCH_OK[3]));
//CAM_RAMB4 CAM_X_RAMB4_4 (.DATA_IN(DATA_IN[7:0]), .ADDR(ADDR[3:0]), WRITE_ENABLE(BUS_WRITE_ENABLE[4]),
// .ERASE_WRITE(ERASE_WRITE), .WRITE_RAM(WRITE_RAM), .CLK(CLK), .MATCH_ENABLE(MATCH_ENABLE),
// .MATCH_RST(MATCH_RST), .MATCH(MATCH_ARRAY_4));
// Generate the Match Address
//ENCODE_4_LSB ENCODE_X_LSB_4 (.BINARY_ADDR(MATCH_ARRAY_4), .MATCH_ADDR(ADDR_ARRAY_4),
// `ifdef use_addr_valid
// .ADDR_VALID(BUS_ADDR_VALID[4]),
// `endif
// .MATCH_OK(BUS_MATCH_OK[4]));
//CAM_RAMB4 CAM_X_RAMB4_5 (.DATA_IN(DATA_IN[7:0]), .ADDR(ADDR[3:0]), WRITE_ENABLE(BUS_WRITE_ENABLE[5]),
// .ERASE_WRITE(ERASE_WRITE), .WRITE_RAM(WRITE_RAM), .CLK(CLK), .MATCH_ENABLE(MATCH_ENABLE),
// .MATCH_RST(MATCH_RST), .MATCH(MATCH_ARRAY_5));
// Generate the Match Address
//ENCODE_4_LSB ENCODE_X_LSB_5 (.BINARY_ADDR(MATCH_ARRAY_5), .MATCH_ADDR(ADDR_ARRAY_5),
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