cam_top.ucf

Using Block RAM for High-Performance Read.Write Cams

#########################################################################################################
# Constraint File for CAM_Top CAM32x8 at 66 MHz (Read and Write)
# VHDL code: JLB
# Synthesis Tools: Synopsys FE 3.2
# UCF: 09/27/99 - JLB
#
# Optional Floorplanning Constraints:
# Init_8_RAM16x1s.vhd needs to be compiled with the RLOC (keep hierarchy)
# - CAM32x8 at 80 MHz (Read and Write)
# - Match RAM access at 200 MHz
#########################################################################################################
# 
# Global Clock Constraint
NET "CLK" TNM_NET = CLK_DLL;
TIMESPEC "TS_CLK" = PERIOD "CLK_DLL" 15 ns;
#
# All Outputs are in Fast mode
NET "O_MATCH_*" FAST;
#
NET "GLOBAL_RST" TIG;
#
# High priority on the DATA nets (High fanout)
NET "DATA_IN<*>" 		MAXDELAY = 4.5 ns;
#
# High priority on the critical net WRITE_RAM
#NET "CAM_generic_8s_1/WRITE_RAM" MAXDELAY = 3ns;
#
#
### Optional Floorplannig:
#
#INST "CAM_generic_8s_1/CAM_X_RAMB4_0/RAMB4/RAMB4"		LOC = "RAMB4_R0C0";
#INST "CAM_generic_8s_1/CAM_X_RAMB4_0/RAM_ERASE/RAM_ERASE_0"	RLOC_ORIGIN = "R1C1";
#
#INST "CAM_generic_8s_1/CAM_X_RAMB4_1/RAMB4/RAMB4"		LOC = "RAMB4_R1C0";
#INST "CAM_generic_8s_1/CAM_X_RAMB4_1/RAM_ERASE/RAM_ERASE_0"	RLOC_ORIGIN = "R5C1";
#
### END ###