readme.txt

Using Block RAM for High-Performance Read.Write Cams

README file: XAPP204 Verilog Reference Design
=============================================

Date: Tuesday December 7, 1999

Designer: Jean-Louis Brelet / Xilinx
Author: Maria George / Xilinx

File Name:
----------
  xapp204_verilog.zip, xapp204_verilog.tar.Z

Description:
------------
  Contains the following files
	readme.doc	: This file

	CAM_Top.ucf	: Alliance Timing Constraints example for a CAM 32 words x 8 bits at 66 MHz 
	
	CAM_top.v : Top Verilog wrapper file for testing CAM_generic_8s.v (Default CAM 32x8)
	CAM_generic_8s.v : Top level of the reference design (Parametrizable word width and depth)
	CAM_RAMB4.v : CAM module 16 x 8-bit
	Init_8_RAM16Xx1s.v : Basic Building block instantiating 8 RAM16x1s
	Init_RAMB4_S1_S16.v : Basic Building Block instantiating RAMB4
	Encode_4_LSB.v : Encode a 16-bit binary address into 4 bits
	Encode_X_MSB.v : (available for 4, 3, 2 and 1 bit) 
			Encode binary address into a X bits bus and add the LSB address
	Decode_X.v : (available for 4, 3, 2 and 1 bit) Decode X bits into a binary address

	TB_CAM_RAMB4.v : Test Bench for the module CAM_RAMB4.v

Platform:
---------
  All

Installation/Use:
-----------------
  Use 'unzip' on the .zip file and 'uncompress' followed by 'tar -xvf' on the .tar.Z file.

Parametrizable Verilog code:
-------------------------
  Edit "parameters.v" 
	Modify the "addr_width" to the required number of address lines (default = 5 address lines)
	Modify the "nb_cam16x8s" to the equivalent number of CAM 16 words blocks (default = 2 blocks)

  Edit "CAM_generic_word.v"
	Remove the comments of the corresponding "Encode_X_MSB" and "Decode_X" instantiation
	By default the CAM 32 x 8 uses the Encode_1_MSB and Decode_1 instances.
(Do NOT change or comment the Encode_4_LSB module, which is required by each basic CAM 16 word module)

Functionnal Simulation:
-----------------------
   The design has been tested using Model Technology ModelSim EE 5.3a
	A testbench for the basic CAM_RAMB4.v is provided as example.

	Create a link to the UNISIM verilog models library. 
	(Please see documentation about functionnal simulation)
	Compile all the verilog files including TB_CAM_RAMB4 (Test Bench)
	Load TB_CAM_RAMB4 and run the simulation. (Basic Write and Read 
operations)

  
Synthesis:
----------
  The design has been tested using Synopsys FPGA Express ver. 3.3
Synthesis option Verilog Pre-processor must be enabled.  The file 
parameters.v should be compiled before all other files.

Additional Information: These files contain the use of the Verilog
                        `ifdef compiler directive.  If the synthesis
                        tool used to compile these files does not
                        support this directive or if major modifications
                        are required to this file, it is suggested that
                        the code first be run through a Verilog
                        Pre-Processor.  Verilog Pre-processors may
                        be found on the Internet as freeware.  Please
                        consult the Verilog FAQ page for locations
                        of Verilog Pre-processors.

Synopsys FPGA Express ver. 3.3:
	In Synthesis -> Options -> Enable Verilog Pre-processor.
	In the "Create Implementation" Template: 
		Device = XCV100EPQ240
		Speed grade = -6
		Preserve Hierarchy = On
		Clock frequency = 66 MHz

	Export Netlist WITHOUT timing 

Implementation:
---------------
   The design has been tested using Xilinx Alliance ver. 2.1i SP3 targetting XCV100 or XCV100E
	(Please see the Alliance 2.1i documentation about how to use the tools)

	Use the "CAM_Top.ucf" file as timing constraints file 
	
	Option: Constraint files with placement are available as example
	(Modify Init_8_RAM16x1s.v module to use RLOC)

	In the "Implementation / Optimize and Map" template:
		Select the Map option = Pack I/O registers into IOB for Inputs & utputs
	Suggested High Place and Route effort

	MAP shows the following warning in the "map.mrp" report file:
	WARNING: Blockcheck: "Dangling BLKRAM output. Pin DOA0 of comp .../RAMB4 is not connected"
	This warning can be ignored because the Block SelectRAM memories have no connection on 
	the port A output. (Use as Write port only)


Who to Contact if you have questions?

http://www.xilinx.com/support/techsup/tappinfo.htm

North American Support
Hotline: [phone] 
or [phone] 
Fax: [phone] 
Email: [e-mail] 
 
United Kingdom Support
Hotline: [phone]
Fax: [phone] 
Email : [e-mail] 
 
France Support
Hotline: [phone] 
Fax: [phone]
Email : [e-mail] 
 
Germany Support
Hotline: [phone] 
Fax: [phone] 
Email : [e-mail] 
 
Japan Support
Hotline: Local Distributor
Fax: Local Distributor
Email: [e-mail]
http://www.xilinx.com/support/techsup/japan.htm