cam_top.v

Using Block RAM for High-Performance Read.Write Cams

//
// Module: 	CAM_Top
// Design: 	CAM_Top
// Verilog code:	Hierarchical wrapper
//		Instantiate CAM_generic_8s (depth variable by 16x8bits word)
//
//
// Description: 	Instantiate a CAM implementation
//		Registered inputs and outputs (CAM internal timing analysis)
//
// Device: 	VIRTEX Family (VIRTEX & VIRTEX-E)
//
// Synthesis_tool	Synopsys FPGA Express ver. 3.3 
//	 	        Enable Synthesis Option: Verilog Pre-procesor
//
//
//
// Device: 	VIRTEX Families
//
// Created by: Jean-Louis BRELET / XILINX - VIRTEX Applications
// Converted to Verilog: Maria George - VIRTEX Applications
// Date: December 8, 1999
// Version: 1.0
//
// History: 
// 	1. 12/08/99 MG - Translated to Verilog
//
//   Disclaimer:  THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY 
//                WHATSOEVER AND XILINX SPECIFICALLY DISCLAIMS ANY 
//                IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR
//                A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT.
//
//  Copyright (c) 1999 Xilinx, Inc.  All rights reserved.
//////////////////////////////////////////////////////////////////////////////////////////////////////-
`include "parameters.v"

//Convension: All I_XXXX are inputs to be registered, O_XXXX are registered Outputs

module CAM_Top (I_DATA_IN,        // Data to be compared or to be written 
                I_ADDR,           // Address when write only
                WRITE_ENABLE,     // Write Enable if HIGH (2 clock cycles)
                I_CLK, 
                GLOBAL_RST,       // Global Asynchronous Reset (GSR resource)
                I_MATCH_ENABLE,   // Enable to find a match, otherwise no change on MATCH bus.
                MATCH_RST,        // If '0' the MATCH bus outputs "0000000000000000" when MATCH_ENABLE ='1'
                O_MATCH_ADDR,     // Match address found
       `ifdef use_addr_valid
                 O_ADDR_VALID,   // '1' when O_MATCH_ADDR is valid
       `endif
                O_MATCH_OK        // '1' if match found
                ); 
                

input [7:0] I_DATA_IN;
input [`addr_width-1:0] I_ADDR;
input WRITE_ENABLE, I_CLK, GLOBAL_RST, I_MATCH_ENABLE, MATCH_RST;
output [`addr_width-1:0] O_MATCH_ADDR;
output O_MATCH_OK;
`ifdef use_addr_valid
        output O_ADDR_VALID;
`endif

reg [`addr_width-1:0] O_MATCH_ADDR;
reg O_MATCH_OK;
`ifdef use_addr_valid
         reg O_ADDR_VALID;
`endif

// Internal Signal Declarations

reg [7:0] DATA_IN;
reg [`addr_width-1:0] ADDR;
reg MATCH_ENABLE;
wire CLK;
reg [`addr_width-1:0] MATCH_ADDR;
reg MATCH_OK;
`ifdef use_addr_valid
         wire ADDR_VALID;
`endif



//reg VCC;
//reg GND;

// assign VCC = 1'b1;
// assign GND = 1'b0;

// Instantiate the DLL

BUFGDLL BUF_DLL (.I(I_CLK), .O(CLK));

//Registered Inputs and Outputs
//REGISTERED_IO
always @ (posedge CLK or posedge GLOBAL_RST)
  begin
    if (GLOBAL_RST)
      begin
        DATA_IN <= 0;
        ADDR <= 0;
        MATCH_ENABLE <= 1'b0;
        O_MATCH_ADDR <= 0;
        O_MATCH_OK <= 1'b0;
        `ifdef use_addr_valid
                 O_ADDR_VALID <= 1'b0;
        `endif
      end // if (GLOBAL_RST)
    else
      begin
        DATA_IN <= I_DATA_IN;
        ADDR <= I_ADDR;
        MATCH_ENABLE <= I_MATCH_ENABLE;
        O_MATCH_ADDR <= MATCH_ADDR;
        O_MATCH_OK <= MATCH_OK;
        `ifdef use_addr_valid
                 O_ADDR_VALID <= ADDR_VALID;
        `endif
      end  // else
  end // REGISTERED_IO
  
  
// Instantiate CAM

CAM_generic_8s CAM_generic_8s_1 (.DATA_IN(DATA_IN),
                                 .ADDR(ADDR),
                                 .WRITE_ENABLE(WRITE_ENABLE),
                                 .CLK(CLK),
                                 .MATCH_ENABLE(MATCH_ENABLE),
                                 .MATCH_RST(MATCH_RST),
                                 .GLOBAL_RST(GLOBAL_RST),
                                 .R_MATCH_ADDR(MATCH_ADDR),
                         `ifdef use_addr_valid
                                 .ADDR_VALID(ADDR_VALID),
                         `endif
                                 .R_MATCH_OK(MATCH_OK));
                                                           
                                                           
endmodule // CAM_Top