cam_ramb4.v

Using Block RAM for High-Performance Read.Write Cams

//
// Module: 	CAM_RAMB4
// Design: 	CAM_Top
// Verilog code:	RTL / Combinatorial
//
// Synthesis_tool	Synopsys FPGA Express ver. 3.3 
//	 	        Enable Synthesis Option: Verilog Pre-procesor
//
// Description: Basic building block of a CAM using Select BlockRAM
//		16 words depth x 8 bits width
//		1 clock Read (or Match), 2 clock Write (Erase on the first clock then Store on the second)
//		If NO match is found the output MATCH<15:0> = "0000000000000000"
//		MATCH bus gives on 16 signals a binary address.
//		Initialized RAM16x1s and RAMB4 in low level module.
//
//
// Device: 	VIRTEX Families
//
// Created by: Jean-Louis BRELET / XILINX - VIRTEX Applications
// Converted to Verilog: Maria George - VIRTEX Applications
// Date: December 8, 1999
// Version: 1.0
//
// History: 
// 	1. 12/08/99 MG - Translated to Verilog
//
//   Disclaimer:  THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY 
//                WHATSOEVER AND XILINX SPECIFICALLY DISCLAIMS ANY 
//                IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR
//                A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT.
//
//  Copyright (c) 1999 Xilinx, Inc.  All rights reserved.
//////////////////////////////////////////////////////////////////////////////////////////////////////-
module CAM_RAMB4 (DATA_IN,          // Data to compare or to write
                  ADDR,             // Used to erase or write operation only
                  WRITE_ENABLE,     // Write Enable during two clock cycles
                  ERASE_WRITE,      // if '0' ERASE else WRITE, generated from 
                                    // WRITE_ENABLE at the CANs' top level
                  WRITE_RAM,        // if '1' DATA_IN is written in the RAM16x1s,
                                    // generated from WRITE_ENABLE at the CAMs' top level
                  CLK,
                  MATCH_ENABLE,
                  MATCH_RST,        // Synchronous reset, causes MATCH="0000000000000000"
                  MATCH);
                  
input [7:0] DATA_IN;
input [3:0] ADDR;
input WRITE_ENABLE;
input ERASE_WRITE;
input WRITE_RAM;
input CLK;
input MATCH_ENABLE;
input MATCH_RST;
output [15:0] MATCH;

// Internal Signal Declarations

wire [7:0] DATA_WRITE;  // Data to be written in the RAMB4
wire [11:0] ADDR_WRITE; // Write Address generated by combining ADDR and DATA_WRITE
wire B_MATCH_RST;       // Inverted MATCH_RST active high

assign B_MATCH_RST = !(MATCH_RST);
assign ADDR_WRITE = {DATA_WRITE, ADDR}; // Combine the DATA_WRITE and the ADDR
                                         // into an address bus

// Instantiate the SelectRAM 8 X RAM16x1s_1

INIT_8_RAM16x1s RAM_ERASE (.DATA_IN(DATA_IN), .ADDR(ADDR), .WRITE_RAM(WRITE_RAM), 
                           .CLK(CLK), .DATA_WRITE(DATA_WRITE));

// Select the write data for addressing
// ERASE mode => DATA_WRITE is read from the RAM16x1s (old value)
// WRITE mode => DATA_WRITE = DATA_IN (new value) is encoded in the RAMB4
                           
                           
// Instantiate the BlockSelectRAM RAMB4_S1_S16 

// For two clock cycles, WRITE_ENABLE = '1'. At the first clock cycle, 
// Port A is ERASE. At second clock cycle Port A is Write.

// Port B is the MATCH port.

INIT_RAMB4_S1_S16 RAMB4 (.DIA(ERASE_WRITE), //First clock cycle ERASE=>write a "0"
                                            //then second clock cycle WRITE=>write a "1"
                         .ENA(WRITE_ENABLE),
                         .ENB(MATCH_ENABLE),
                         .WEA(WRITE_ENABLE),
                         .RSTB(B_MATCH_RST),
                         .CLK(CLK),
                         .ADDRA(ADDR_WRITE),
                         .ADDRB(DATA_IN),
                         .DOB(MATCH));
                         
                         
endmodule  // CAM_RAMB4