cam_ramb4.vhd

Using Block RAM for High-Performance Read.Write Cams

--
-- Module: 	CAM_RAMB4
-- Design: 	CAM_Top
-- VHDL code:	Hierarchical RTL
--			Instantiate INIT_RAMB4_S1_S16
--			Instantiate INIT_8_RAM16x1s
--
-- Synthesis	Synopsys FPGA Express ver. 3.2 
--		Use of "pragma synthesis_off/on" and attributes
--
-- Description: Basic building block of a CAM using Select BlockRAM
--		16 words depth x 8 bits width
--		1 clock Read (or Match), 2 clock Write (Erase on the first clock then Store on the second)
--		If NO match is found the output MATCH<15:0> = "0000000000000000"
--		MATCH bus gives on 16 signals a binary address.
--		Initialized RAM16x1s and RAMB4 in low level module
--
-- Device: 	VIRTEX Family (VIRTEX & VIRTEX-E)
--
-- Created by: Jean-Louis BRELET / XILINX - VIRTEX Applications
-- Date: July 29, 1999
-- Version: 1.0
--
-- History: 
-- 	1.
--
--   Disclaimer:  THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY 
--                WHATSOEVER AND XILINX SPECIFICALLY DISCLAIMS ANY 
--                IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR
--                A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT.
--
--  Copyright (c) 1999 Xilinx, Inc.  All rights reserved.
-------------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;

-- Syntax for Synopsys FPGA Express
-- pragma translate_off
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
-- pragma translate_on


entity CAM_RAMB4 is
    port (
	DATA_IN	: in std_logic_vector(7 downto 0) ; -- Data to compare or to write
	ADDR		: in std_logic_vector(3 downto 0) ; -- Used by erase/write operation only
	WRITE_ENABLE	: in std_logic; -- Write Enable during 2 clock cycles
	ERASE_WRITE	: in std_logic; -- if '0' ERASE else WRITE, generate from WRITE_ENABLE at the CAMs' top level
	WRITE_RAM	: in std_logic; -- if '1' DATA_IN is WRITE in the RAM16x1s, generate from WRITE_ENABLE at the CAMs' top level	
	CLK		: in std_logic;
	MATCH_ENABLE	: in std_logic;
	MATCH_RST	: in std_logic; -- Synchronous reset => MATCH = "00000000000000000"
	MATCH		: out std_logic_vector(15 downto 0) 
	);
end CAM_RAMB4;

architecture CAM_RAMB4_arch of CAM_RAMB4 is
--
-- Components Declarations:
component INIT_8_RAM16x1s
    port (
	DATA_IN	: in std_logic_vector(7 downto 0);
	ADDR		: in std_logic_vector(3 downto 0);
	WRITE_RAM	: in std_logic;
	CLK		: in std_logic;
	DATA_WRITE	: out std_logic_vector(7 downto 0)
    );
end component;
	
component INIT_RAMB4_S1_S16 
    port (
	DIA   	: in std_logic;
	ENA   	: in std_logic;
	ENB   	: in std_logic;
	WEA    	: in std_logic;
	RSTB   	: in std_logic;
	CLK   	: in std_logic;
	ADDRA 	: in std_logic_vector (11 downto 0);
	ADDRB  	: in std_logic_vector (7 downto 0);
	DOB   	: out std_logic_vector (15 downto 0)
    ); 
end component;
--
-- Signal Declarations:
--
signal DATA_WRITE : std_logic_vector(7 downto 0);	-- Data to be written in the RAMB4
signal ADDR_WRITE : std_logic_vector(11 downto 0);	-- Combine write address from ADDR and DATA_WRITE
signal B_MATCH_RST: std_logic; -- inverter MATCH_RST active high
-- signal VCC : std_logic;
-- signal GND : std_logic;
--
begin
-- VCC <= '1';
-- GND <= '0';

B_MATCH_RST <= not MATCH_RST;

-- SelectRAM instantiation = 8 x RAM16x1s_1
RAM_ERASE: INIT_8_RAM16x1s 
	port map (
	DATA_IN => DATA_IN,
	ADDR => ADDR,
	WRITE_RAM => WRITE_RAM,
	CLK => CLK,
	DATA_WRITE => DATA_WRITE
	);
--
-- Select the write data for addressing
-- ERASE mode => DATA_WRITE is read from the RAM16x1s (old value)
-- WRITE mode => DATA_WRITE = DATA_IN (new value) is encoded in the RAMB4

-- Combine the DATA_WRITE<7:0> and ADDR<3:0> into an address bus
ADDR_WRITE(3 downto 0) <= ADDR(3 downto 0);
ADDR_WRITE(11 downto 4) <= DATA_WRITE(7 downto 0);

-- Select BlockRAM RAMB4_S1_S16 instantiation
-- Port A is the Erase (first clock cycle when WRITE_ENABLE = '1') then Write (second clock cycle when WRITE_ENABLE ='1')
-- Port B is the Match 
RAMB4 : INIT_RAMB4_S1_S16 
	port map (
	DIA => ERASE_WRITE,  -- First clock cycle Erase => write a "0" then second clock cycle => write a "1"
	ENA => WRITE_ENABLE,
	ENB => MATCH_ENABLE,
	WEA => WRITE_ENABLE,
	RSTB => B_MATCH_RST,
	CLK => CLK,
	ADDRA => ADDR_WRITE(11 downto 0),
	ADDRB => DATA_IN(7 downto 0),
	DOB => MATCH(15 downto 0) 
		);
		
end CAM_RAMB4_arch;