cam_generic_8s.vhd

Using Block RAM for High-Performance Read.Write Cams

--
-- Module: 	CAM_generic_8s
-- Design: 	CAM_Top
-- VHDL code:	Hierarchical RTL
--			Instantiate CAM_RAMB4
--				Instantiate INIT_RAMB4_S1_S16
--				Instantiate INIT_8_RAM16x1s
--			Instantiate ENCODE_4_LSB
--			Instantiate DECODE_X
--			Instantiate ENCODE_X_MSB
--		Choice the right ENCODE and DECODE modules according to the number of CAM16x8s
--		If "nb_cam16x8s" = 2 then ENCODE_1_MSB and DECODE_1 must be used: 1 bit to decode 2 CAM16x8s
--		If "nb_cam16x8s" = 4 then ENCODE_2_MSB and DECODE_2 must be used: 2 bits to decode 4 CAM16x8s
--		If "nb_cam16x8s" = 8 then ENCODE_3_MSB and DECODE_3 must be used: 3 bits to decode 8 CAM16x8s
--		If "nb_cam16x8s" = 16 then ENCODE_4_MSB and DECODE_4 must be used: 4 bits to decode 16 CAM16x8s
--		Note: Configuration is not supported by synthesis tools
--
-- Synthesis	Synopsys FPGA Express ver. 3.2  - Option = Preserve Hierarchy
--		Use of "pragma synthesis_off/on" and attributes
--
-- Description: Instantiate "nb_cam16x8s" CAM_RAMB4 (see generic)
--		"nb_cam16x8s" x 16 words depth x 8 bits width
--		1 clock cycle Read (or Match), 
--		2 clock cycles Write (Erase on the first clock then Store on the second) / If only 1 clock cycle => Erase Only.
--		MATCH_OK indicates one or more matches is/are found.
--		MATCH_ADDR ouput the address of the match, if ONLY ONE is found
--		ADDR_VALID indicates when MATCH_ADDR is a valid address (Optional)
--
-- Device: 	VIRTEX Family (VIRTEX & VIRTEX-E)
--		modules CAM_RAMB4 fits in 1 BlockRAM column (+ CLB)
--		If "nb_cam16x8s" = 4 then  CAM64x8s (fits in 1 XCV50 or XCV50E BlockRam Column)
--		If "nb_cam16x8s" = 8 then  CAM128x8s (fits in 1 XCV300 or XCV300E BlockRam Column)
--		If "nb_cam16x8s" = 16 then  CAM256x8s (fits in 1 XCV1000 or XCV1000E BlockRam Column)
--
-- Created by: Jean-Louis BRELET / XILINX - VIRTEX Applications
-- Date: July 29, 1999
-- Version: 1.0
--
-- History: 
-- 	1.JLB-9/13/99: Update ERASE_WRITE and WRITE_RAM generation
--
--   Disclaimer:  THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY 
--                WHATSOEVER AND XILINX SPECIFICALLY DISCLAIMS ANY 
--                IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR
--                A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT.
--
--  Copyright (c) 1999 Xilinx, Inc.  All rights reserved.
-------------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;

-- Syntax for Synopsys FPGA Express
-- pragma translate_off
--library UNISIM;
--use UNISIM.VCOMPONENTS.ALL;
-- pragma translate_on

entity CAM_generic_8s is
   generic (
        addr_width 	: integer; -- 5; -- CAM 32 words / 6; -- CAM 64 words / 7; -- CAM 128 words / 8; -- CAM 256 words
        nb_cam16x8s	: integer -- 2 -- CAM 2 x16 = 32 / 4 -- CAM 4x16 = 64 / 8 -- CAM 8x16 = 128 / 16 -- CAM 16x16 = 256   
    );
    port (
        DATA_IN		: in std_logic_vector (7 downto 0); -- Data to compare or to write
        ADDR		: in std_logic_vector (addr_width-1 downto 0); -- Address when write ONLY
        WRITE_ENABLE	: in std_logic; -- Write Enable if High (2 clock cycles)
        CLK		: in std_logic;
        MATCH_ENABLE	: in std_logic; -- Enable to find a match, otherwise No change on MATCH bus.
        MATCH_RST	: in std_logic; -- If '0' the MATCH bus outputs "0000000000000000" when MATCH_ENABLE = '1' (Synchronous)
        GLOBAL_RST	: in std_logic; -- Global Asynchronous FF Reset
        R_MATCH_ADDR	: out std_logic_vector (addr_width-1 downto 0); -- Registered Match address found
        R_MATCH_OK	: out std_logic -- '1' if MATCH found / Registered
--        ADDR_VALID	: out std_logic (Double the size of the encoder. Need ONLY if simultaneous matches can occur !) Optional
    );
end CAM_generic_8s;

architecture CAM_generic_8s_arch of CAM_generic_8s is
--
-- Components Declarations:
--
component CAM_RAMB4 	
    port (
        DATA_IN		: in std_logic_vector (7 downto 0);	
        ADDR		: in std_logic_vector (3 downto 0);
        WRITE_ENABLE	: in std_logic;	
        ERASE_WRITE	: in std_logic;
        WRITE_RAM	: in std_logic;			
        CLK			: in std_logic;
        MATCH_ENABLE	: in std_logic;		
        MATCH_RST	: in std_logic;		
        MATCH		: out std_logic_vector (15 downto 0)
    );
end component;
--
component ENCODE_4_LSB
   port (
        BINARY_ADDR	: in std_logic_vector(15 downto 0);
        MATCH_ADDR	: out std_logic_vector(3 downto 0);
-- Optional --       ADDR_VALID	: out std_logic; 
        MATCH_OK		: out std_logic
    );   
end component;
--
component ENCODE_1_MSB
	port (
	BINARY_ADDR	: in std_logic_vector(nb_cam16x8s-1 downto 0);
	ADDR_LSB_0 	: in std_logic_vector(3 downto 0); 
	ADDR_LSB_1 	: in std_logic_vector(3 downto 0);
	MATCH_ADDR	: out std_logic_vector(addr_width-1 downto 0);
-- Optional --	ADDR_VALID	: out std_logic;
	MATCH_OK	: out std_logic
	);
end component;
--
component ENCODE_2_MSB
	port (
	BINARY_ADDR	: in std_logic_vector(nb_cam16x8s-1 downto 0);
	ADDR_LSB_0 	: in std_logic_vector(3 downto 0); 
	ADDR_LSB_1 	: in std_logic_vector(3 downto 0);
 	ADDR_LSB_2 	: in std_logic_vector(3 downto 0); 
	ADDR_LSB_3 	: in std_logic_vector(3 downto 0);
	MATCH_ADDR	: out std_logic_vector(addr_width-1 downto 0);
-- Optional --	ADDR_VALID	: out std_logic;
	MATCH_OK	: out std_logic
	);
end component;
--
component ENCODE_3_MSB
	port (
	BINARY_ADDR	: in std_logic_vector(nb_cam16x8s-1 downto 0);
	ADDR_LSB_0 	: in std_logic_vector(3 downto 0); 
	ADDR_LSB_1 	: in std_logic_vector(3 downto 0);
 	ADDR_LSB_2 	: in std_logic_vector(3 downto 0); 
	ADDR_LSB_3 	: in std_logic_vector(3 downto 0);
 	ADDR_LSB_4 	: in std_logic_vector(3 downto 0); 
	ADDR_LSB_5 	: in std_logic_vector(3 downto 0);
	ADDR_LSB_6 	: in std_logic_vector(3 downto 0); 
	ADDR_LSB_7 	: in std_logic_vector(3 downto 0);	
             	MATCH_ADDR	: out std_logic_vector(addr_width-1 downto 0);
-- Optional --	ADDR_VALID	: out std_logic;
	MATCH_OK	: out std_logic
	);
end component;
--
component ENCODE_4_MSB
	port (
	BINARY_ADDR	: in std_logic_vector(nb_cam16x8s-1 downto 0);
	ADDR_LSB_0 	: in std_logic_vector(3 downto 0); 
	ADDR_LSB_1 	: in std_logic_vector(3 downto 0);
 	ADDR_LSB_2 	: in std_logic_vector(3 downto 0); 
	ADDR_LSB_3 	: in std_logic_vector(3 downto 0);
 	ADDR_LSB_4 	: in std_logic_vector(3 downto 0); 
	ADDR_LSB_5 	: in std_logic_vector(3 downto 0);
	ADDR_LSB_6 	: in std_logic_vector(3 downto 0); 
	ADDR_LSB_7 	: in std_logic_vector(3 downto 0);	
	ADDR_LSB_8 	: in std_logic_vector(3 downto 0); 
	ADDR_LSB_9 	: in std_logic_vector(3 downto 0);
 	ADDR_LSB_10 	: in std_logic_vector(3 downto 0); 
	ADDR_LSB_11 	: in std_logic_vector(3 downto 0);
 	ADDR_LSB_12 	: in std_logic_vector(3 downto 0); 
	ADDR_LSB_13 	: in std_logic_vector(3 downto 0);
	ADDR_LSB_14 	: in std_logic_vector(3 downto 0); 
	ADDR_LSB_15 	: in std_logic_vector(3 downto 0);		                            
	MATCH_ADDR	: out std_logic_vector(addr_width-1 downto 0);
-- Optional --	ADDR_VALID	: out std_logic;
	MATCH_OK	: out std_logic
	);
end component;
--
component DECODE_1 
    port (
        ADDR		: in std_logic_vector (addr_width-5 downto 0);
        ENABLE		: in std_logic;
        BINARY_ADDR	: out std_logic_vector (nb_cam16x8s-1 downto 0)
    );
end component;
--
component DECODE_2 
    port (
        ADDR		: in std_logic_vector (addr_width-5 downto 0);
        ENABLE		: in std_logic;
        BINARY_ADDR	: out std_logic_vector (nb_cam16x8s-1 downto 0)
    );
end component;
--
component DECODE_3 
    port (
        ADDR		: in std_logic_vector (addr_width-5 downto 0);
        ENABLE		: in std_logic;
        BINARY_ADDR	: out std_logic_vector (nb_cam16x8s-1 downto 0)
    );
end component;
--
component DECODE_4 
    port (
        ADDR		: in std_logic_vector (addr_width-5 downto 0);
        ENABLE		: in std_logic;
        BINARY_ADDR	: out std_logic_vector (nb_cam16x8s-1 downto 0)
    );
end component;
--
-- Signal Declarations:
signal ERASE_WRITE	 	: std_logic; -- Erase than Write Enable (2 clock cycles)
signal WRITE_RAM 		: std_logic; -- Write enable in the RAM16x1s 
signal BUS_WRITE_ENABLE 	: std_logic_vector (nb_cam16x8s-1 downto 0); -- decode the CAM16x1s to be addressed
-- signal BUS_ADDR_VALID		: std_logic_vector (addr_width-1 downto 0); -- optional
signal BUS_MATCH_OK		: std_logic_vector (nb_cam16x8s-1 downto 0);
--
type type_match_array is array (0 to nb_cam16x8s-1) of std_logic_vector (15 downto 0);
signal MATCH_ARRAY		: type_match_array;
--
type type_addr_array is array (0 to nb_cam16x8s-1) of std_logic_vector (3 downto 0);
signal ADDR_ARRAY		: type_addr_array;
--
signal MATCH_ADDR		: std_logic_vector (addr_width-1 downto 0); -- Match address found
signal MATCH_OK		: std_logic; -- '1' if MATCH found

-- signal VCC : std_logic;
-- signal GND : std_logic;
--
begin
-- VCC <= '1';
-- GND <= '0';

-- In "write Enable" mode, the first clock cycle erase the data, then the 2nd clock cycle write the new data.
-- A one clock cycle WRITE_ENABLE erases ONLY the data. 
-- RAM16x1s are read to erase the RAMB4 ONLY, used to find a match.
-- Doesn't care if the data is not erased in the RAM16x1s
--
-- Generate a Write Enable for the RAM16x1s
CYCLE_ERASE: process (GLOBAL_RST, MATCH_RST, CLK)
begin
	if ( GLOBAL_RST = '1') then 		-- Asynchronous Clear
		WRITE_RAM <= '0';
	elsif (CLK'event and CLK = '0') then 
		if (WRITE_ENABLE = '0') then
			WRITE_RAM <= '0';
		else
			WRITE_RAM <= not(WRITE_RAM);
		end if;
	end if;	
end process CYCLE_ERASE;

-- Generate a Erase signal '0' then a Write signal '1' for the RAMB4 
-- If WRITE_ENABLE is deasserted after 1 clock cycle, the WRITE is not valid (WRITE_ENABLE is used on WEA port)
ERASE_WRITE <= not(WRITE_RAM);
--
-- Create the write enable signal for each CAM_RAMB4 = CAM 32 words
DECODE_X: DECODE_1
	port map (
	ADDR => ADDR(addr_width-1 downto 4),
	ENABLE => WRITE_ENABLE,
	BINARY_ADDR => BUS_WRITE_ENABLE
	);	
--
-- Create the write enable signal for each CAM_RAMB4 = CAM 64 words
--DECODE_X: DECODE_2
--	port map (
--	ADDR => ADDR(addr_width-1 downto 4),
--	ENABLE => WRITE_ENABLE,
--	BINARY_ADDR => BUS_WRITE_ENABLE
--	);	
--
-- Create the write enable signal for each CAM_RAMB4 = CAM 128 words
--DECODE_X: DECODE_3
--	port map (
--	ADDR => ADDR(addr_width-1 downto 4),
--	ENABLE => WRITE_ENABLE,
--	BINARY_ADDR => BUS_WRITE_ENABLE
--	);	
--
-- Create the write enable signal for each CAM_RAMB4 = CAM 256 words
--DECODE_X: DECODE_4
--	port map (
--	ADDR => ADDR(addr_width-1 downto 4),
--	ENABLE => WRITE_ENABLE,
--	BINARY_ADDR => BUS_WRITE_ENABLE
--	);	
--
-- CAM_RAMB4 and ENCODE_X_LSB instantiation 
CAM_RAMB4_X: for i in 0 to nb_cam16x8s-1 generate 
CAM_X_RAMB4 : CAM_RAMB4
        port map (
        DATA_IN => DATA_IN(7 downto 0),
        ADDR => ADDR (3 downto 0),
        WRITE_ENABLE => BUS_WRITE_ENABLE(i),
        ERASE_WRITE => ERASE_WRITE,
        WRITE_RAM => WRITE_RAM,
        CLK => CLK,
        MATCH_ENABLE => MATCH_ENABLE,
        MATCH_RST => MATCH_RST,
        MATCH => MATCH_ARRAY(i)
    );
-- Generate the Match address
ENCODE_X_LSB : ENCODE_4_LSB
      	port map (
	BINARY_ADDR => MATCH_ARRAY(i),
	MATCH_ADDR => ADDR_ARRAY(i),
-- Optional --	ADDR_VALID => BUS_ADDR_VALID(i),
	MATCH_OK => BUS_MATCH_OK(i)
	);
end generate;
--
-- Generate Top address CAM 32 words
ENCODE_X_MSB:  ENCODE_1_MSB
	port map (
	BINARY_ADDR => BUS_MATCH_OK,
	ADDR_LSB_0 => ADDR_ARRAY(0),
	ADDR_LSB_1 => ADDR_ARRAY(1), 
	MATCH_ADDR => MATCH_ADDR(addr_width-1 downto 0),
-- Optional --	ADDR_VALID => ADDR_VALID,
	MATCH_OK => MATCH_OK
	);
-- Generate Top address CAM 64 words
--ENCODE_X_MSB:  ENCODE_2_MSB
--	port map (
--	BINARY_ADDR => BUS_MATCH_OK,
--	ADDR_LSB_0 => ADDR_ARRAY(0),
--	ADDR_LSB_1 => ADDR_ARRAY(1), 
--	ADDR_LSB_2 => ADDR_ARRAY(2), 
--	ADDR_LSB_3 => ADDR_ARRAY(3), 
--	MATCH_ADDR => MATCH_ADDR(addr_width-1 downto 0),
-- Optional --	ADDR_VALID => ADDR_VALID,
--	MATCH_OK => MATCH_OK
--	);
--
-- Generate Top address CAM 128 words
--ENCODE_X_MSB:  ENCODE_3_MSB
--	port map (
--	BINARY_ADDR => BUS_MATCH_OK,
--	ADDR_LSB_0 => ADDR_ARRAY(0),
--	ADDR_LSB_1 => ADDR_ARRAY(1), 
--	ADDR_LSB_2 => ADDR_ARRAY(2), 
--	ADDR_LSB_3 => ADDR_ARRAY(3), 
--	ADDR_LSB_4 => ADDR_ARRAY(4),
--	ADDR_LSB_5 => ADDR_ARRAY(5), 
--	ADDR_LSB_6 => ADDR_ARRAY(6), 
--	ADDR_LSB_7 => ADDR_ARRAY(7),	
--	MATCH_ADDR => MATCH_ADDR(addr_width-1 downto 0),
-- Optional --	ADDR_VALID => ADDR_VALID,
--	MATCH_OK => MATCH_OK
--	);
--
-- Generate Top address CAM 256 words
--ENCODE_X_MSB:  ENCODE_4_MSB
--	port map (
--	BINARY_ADDR => BUS_MATCH_OK,
--	ADDR_LSB_0 => ADDR_ARRAY(0),
--	ADDR_LSB_1 => ADDR_ARRAY(1), 
--	ADDR_LSB_2 => ADDR_ARRAY(2), 
--	ADDR_LSB_3 => ADDR_ARRAY(3), 
--	ADDR_LSB_4 => ADDR_ARRAY(4),
--	ADDR_LSB_5 => ADDR_ARRAY(5), 
--	ADDR_LSB_6 => ADDR_ARRAY(6), 
--	ADDR_LSB_7 => ADDR_ARRAY(7),	
--	ADDR_LSB_8 => ADDR_ARRAY(8),
--	ADDR_LSB_9 => ADDR_ARRAY(9),
--	ADDR_LSB_10 => ADDR_ARRAY(10), 
--	ADDR_LSB_11 => ADDR_ARRAY(11),
--	ADDR_LSB_12 => ADDR_ARRAY(12),
--	ADDR_LSB_13 => ADDR_ARRAY(13),
--	ADDR_LSB_14 => ADDR_ARRAY(14),
--	ADDR_LSB_15 => ADDR_ARRAY(15), 		                            
--	MATCH_ADDR => MATCH_ADDR(addr_width-1 downto 0),
-- Optional --	ADDR_VALID => ADDR_VALID,
--	MATCH_OK => MATCH_OK
--	);
--
-- Registered Outputs
-- Registered inputs and outputs
REGISTERED_OUTPUTS: process (GLOBAL_RST, CLK)
begin
	if ( GLOBAL_RST = '1') then
		R_MATCH_ADDR <= (others => '0');
		R_MATCH_OK <= '0';
	else
		if (CLK'event and CLK = '1') then 
			R_MATCH_ADDR <= MATCH_ADDR;
			R_MATCH_OK <= MATCH_OK;
		end if;
	end if;
end process REGISTERED_OUTPUTS;
--									
end CAM_generic_8s_arch;