encode_3_msb.vhd

Using Block RAM for High-Performance Read.Write Cams

--
-- Module: 	ENCODE_3_MSB
-- Design: 	CAM_Top
-- VHDL code:	RTL / Combinatorial
--
-- Synthesis	Synopsys FPGA Express ver. 3.2 
--		Use of "pragma synthesis_off/on" and attributes
--
-- Description: Encode a 8 bits binary address into 3 bits, map with the LSB address and find if a match occurs
--		if BINARY_ADDR = "00100000" => MATCH_ADDR = "101" / MATCH_OK = 1 
--		Optional ADDR_VALID = 1 when only one Match (If simultaneous matches can occur)
--		However, the ADDR_VALID generation double the size of the combinatorial logic !
--		if no match found => MATCH_OK = 0 / ADDR_VALID = 0 (MATCH_ADDR is not a valid address)
--		if 2 or more matches found => MATCH_OK = 1 / ADDR_VALID = 0 (MATCH_ADDR is not valid address)
--
--		Choice between GATES ONLY implementation or BUFT implementation. (See comments)
--		Note: Configuration is not supported by synthesis tools
--
-- Device: 	VIRTEX Family (VIRTEX & VIRTEX-E)
--
-- Created by: Jean-Louis BRELET / XILINX - VIRTEX Applications
-- Date: July 23, 1999
-- Version: 1.0
--
-- History: 
-- 	1. 
--
--   Disclaimer:  THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY 
--                WHATSOEVER AND XILINX SPECIFICALLY DISCLAIMS ANY 
--                IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR
--                A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT.
--
--  Copyright (c) 1999 Xilinx, Inc.  All rights reserved.
-------------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;

-- Syntax for Synopsys FPGA Express
-- pragma translate_off
--library UNISIM;
--use UNISIM.VCOMPONENTS.ALL;
-- pragma translate_on

entity ENCODE_3_MSB is
	port (
	BINARY_ADDR	: in std_logic_vector(7 downto 0);
	ADDR_LSB_0 	: in std_logic_vector(3 downto 0); 
	ADDR_LSB_1 	: in std_logic_vector(3 downto 0);
 	ADDR_LSB_2 	: in std_logic_vector(3 downto 0); 
	ADDR_LSB_3 	: in std_logic_vector(3 downto 0);
 	ADDR_LSB_4 	: in std_logic_vector(3 downto 0); 
	ADDR_LSB_5 	: in std_logic_vector(3 downto 0);
	ADDR_LSB_6 	: in std_logic_vector(3 downto 0); 
	ADDR_LSB_7 	: in std_logic_vector(3 downto 0);	
    	MATCH_ADDR	: out std_logic_vector(6 downto 0); -- Match address found
--	ADDR_VALID	: out std_logic; -- '1' if MATCH_ADDR is valid (Only one match)
	MATCH_OK	: out std_logic -- '1' if MATCH found
	);
end ENCODE_3_MSB;

architecture ENCODE_3_MSB_arch of ENCODE_3_MSB is
--
-- Components Declarations:
--
-- Signal Declarations:
-- signal VCC : std_logic;
-- signal GND : std_logic;
--
begin
-- VCC <= '1';
-- GND <= '0';
--
-- Convert the binary address in an address bus, ONLY is ONE match is found
-- Optional ADDR_VALID signal generation double the logic size of the encoder !!!
--
-- Choice between gates only implementation or BUFT implementation.
--
-- Begin GATES ONLY implementation --
-- GENERATE_MSB_ADDRESS : process (BINARY_ADDR, ADDR_LSB_0, ADDR_LSB_1, ADDR_LSB_2, ADDR_LSB_3,
--						ADDR_LSB_4, ADDR_LSB_5, ADDR_LSB_6, ADDR_LSB_7)
-- begin
--	Optional -- ADDR_VALID <= '1';
--	case BINARY_ADDR(7 downto 0) is	
--		when "00000001" => MATCH_ADDR(6 downto 0)<= "000" & ADDR_LSB_0(3 downto 0);
--		when "00000010" => MATCH_ADDR(6 downto 0)<= "001" & ADDR_LSB_1(3 downto 0);
--		when "00000100" => MATCH_ADDR(6 downto 0)<= "010" & ADDR_LSB_2(3 downto 0);
--		when "00001000" => MATCH_ADDR(6 downto 0)<= "011" & ADDR_LSB_3(3 downto 0);
--		when "00010000" => MATCH_ADDR(6 downto 0)<= "100" & ADDR_LSB_4(3 downto 0);
--		when "00100000" => MATCH_ADDR(6 downto 0)<= "101" & ADDR_LSB_5(3 downto 0);
--		when "01000000" => MATCH_ADDR(6 downto 0)<= "110" & ADDR_LSB_6(3 downto 0);
--		when "10000000" => MATCH_ADDR(6 downto 0)<= "111" & ADDR_LSB_7(3 downto 0);
--		when others => 
--			MATCH_ADDR(6 downto 0)<= ( others => 'X');										
--	Optional --		ADDR_VALID <= '0';
--	end case;
-- end process GENERATE_MSB_ADDRESS;
-- End GATES ONLY implementation --
--
-- Begin BUFT implementation --
-- 2  statements are used to implement the LSB address in BUFT (mux 8:1) and MSB in gates (MATCH_ADDR(6 downto 0) <= "xxx" & ADDR_LSB_X);
GENERATE_MSB_ADDRESS : process (BINARY_ADDR)
begin
--	Optional -- ADDR_VALID <= '1';
	case BINARY_ADDR(7 downto 0) is	
		when "00000001" => MATCH_ADDR(6 downto 4)<= "000";
		when "00000010" => MATCH_ADDR(6 downto 4)<= "001";
		when "00000100" => MATCH_ADDR(6 downto 4)<= "010";
		when "00001000" => MATCH_ADDR(6 downto 4)<= "011";
		when "00010000" => MATCH_ADDR(6 downto 4)<= "100";
		when "00100000" => MATCH_ADDR(6 downto 4)<= "101";
		when "01000000" => MATCH_ADDR(6 downto 4)<= "110";
		when "10000000" => MATCH_ADDR(6 downto 4)<= "111";
		when others => 
			MATCH_ADDR(6 downto 4)<= ( others => 'X');										
--	Optional --		ADDR_VALID <= '0';
	end case;
end process GENERATE_MSB_ADDRESS;

-- Infer Tri-State Buffers Muxes 8:1
INFER_TBUF_MUX: for i in 0 to 3 generate 
	MATCH_ADDR(i) <= ADDR_LSB_0(i) when BINARY_ADDR(0) = '1' else 'Z';
	MATCH_ADDR(i) <= ADDR_LSB_1(i)  when BINARY_ADDR(1) = '1' else 'Z';
	MATCH_ADDR(i) <= ADDR_LSB_2(i) when BINARY_ADDR(2) = '1' else 'Z';
	MATCH_ADDR(i) <= ADDR_LSB_3(i) when BINARY_ADDR(3) = '1' else 'Z';
	MATCH_ADDR(i) <= ADDR_LSB_4(i) when BINARY_ADDR(4) = '1' else 'Z';
	MATCH_ADDR(i) <= ADDR_LSB_5(i) when BINARY_ADDR(5) = '1' else 'Z';
	MATCH_ADDR(i) <= ADDR_LSB_6(i) when BINARY_ADDR(6) = '1' else 'Z';
	MATCH_ADDR(i) <= ADDR_LSB_7(i) when BINARY_ADDR(7) = '1' else 'Z';
end generate ;
-- End BUFT implementation --
--
-- Generate the match signal if one or more matche(s) is/are found
GENERATE_MATCH : process (BINARY_ADDR)
begin
if (BINARY_ADDR = "00000000") then
	MATCH_OK <= '0';
else
	MATCH_OK <= '1';
end if;
end process GENERATE_MATCH;

end ENCODE_3_MSB_arch;