encode_4_lsb.vhd

Using Block RAM for High-Performance Read.Write Cams

--
-- Module: 	ENCODE_4_LSB
-- Design: 	CAM_Top
-- VHDL code:	RTL / Combinatorial
--
-- Synthesis	Synopsys FPGA Express ver. 3.2 
--		Use of "pragma synthesis_off/on" and attributes
--
-- Description: Encode a 16 bits binary address into 4 bits and find if a match occurs
--		if BINARY_ADDR = "0000000000100000" => MATCH_ADDR = "0101" / MATCH_OK = 1 
--		Optional ADDR_VALID = 1 when only one Match (If simultaneous matches can occur)
--		However, the ADDR_VALID generation double the size of the combinatorial logic !
--		if no match found => MATCH_OK = 0 / ADDR_VALID = 0 (MATCH_ADDR is not a valid address)
--		if 2 or more matches found => MATCH_OK = 1 / ADDR_VALID = 0 (MATCH_ADDR is not valid address)
--
-- Device: 	VIRTEX Family (VIRTEX & VIRTEX-E)
--
-- Created by: Jean-Louis BRELET / XILINX - VIRTEX Applications
-- Date: July 23, 1999
-- Version: 1.0
--
-- History: 
-- 	1. 
--
--   Disclaimer:  THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY 
--                WHATSOEVER AND XILINX SPECIFICALLY DISCLAIMS ANY 
--                IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR
--                A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT.
--
--  Copyright (c) 1999 Xilinx, Inc.  All rights reserved.
-------------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;

-- Syntax for Synopsys FPGA Express
-- pragma translate_off
--library UNISIM;
--use UNISIM.VCOMPONENTS.ALL;
-- pragma translate_on

entity ENCODE_4_LSB is
    port (
        BINARY_ADDR	: in std_logic_vector(15 downto 0);
        MATCH_ADDR	: out std_logic_vector(3 downto 0); -- Match address found
--       ADDR_VALID	: out std_logic; -- '1' if MATCH_ADDR is valid (Only one match)
        MATCH_OK		: out std_logic -- '1' if MATCH found
    );
end ENCODE_4_LSB;

architecture ENCODE_4_LSB_arch of ENCODE_4_LSB is
--
-- Components Declarations:
--
-- Signal Declarations:
-- signal VCC : std_logic;
-- signal GND : std_logic;
--
begin
-- VCC <= '1';
-- GND <= '0';

-- Convert the binary address in an address bus, ONLY is ONE match is found
-- ADDR_VALID signal generation double the logic size of the encoder !!!
GENERATE_ADDRESS : process (BINARY_ADDR)
begin
--	ADDR_VALID <= '1';
	case BINARY_ADDR(15 downto 0) is	
		when "0000000000000001" => MATCH_ADDR <= "0000";
		when "0000000000000010" => MATCH_ADDR <= "0001";
		when "0000000000000100" => MATCH_ADDR <= "0010";
		when "0000000000001000" => MATCH_ADDR <= "0011";
		when "0000000000010000" => MATCH_ADDR <= "0100";
		when "0000000000100000" => MATCH_ADDR <= "0101";
		when "0000000001000000" => MATCH_ADDR <= "0110";
		when "0000000010000000" => MATCH_ADDR <= "0111";
		when "0000000100000000" => MATCH_ADDR <= "1000";
		when "0000001000000000" => MATCH_ADDR <= "1001";
		when "0000010000000000" => MATCH_ADDR <= "1010";
		when "0000100000000000" => MATCH_ADDR <= "1011";
		when "0001000000000000" => MATCH_ADDR <= "1100";
		when "0010000000000000" => MATCH_ADDR <= "1101";
		when "0100000000000000" => MATCH_ADDR <= "1110";
		when "1000000000000000" => MATCH_ADDR <= "1111";
		when others => 
			MATCH_ADDR <= ( others => 'X');										
--			ADDR_VALID <= '0';
	end case;
end process GENERATE_ADDRESS;

-- Generate the match signal if one or more matche(s) is/are found
GENERATE_MATCH : process (BINARY_ADDR)
begin
if (BINARY_ADDR = "0000000000000000") then
	MATCH_OK <= '0';
else
	MATCH_OK <= '1';
end if;
end process GENERATE_MATCH;

end ENCODE_4_LSB_arch;