tb_cam_ramb4.vhd

Using Block RAM for High-Performance Read.Write Cams

--
-- Module: 	TB_CAM_RAMB4
-- Design: 	Test Bench for CAM_RAMB4
-- VHDL code:	Test vectors 
--			Instantiate CAM_RAMB4
--
-- Simulation	ModelSim EE v5.2e
--
-- Description: Read mode
--		Write mode
--		Multi-Matches 
--
-- Device: 	VIRTEX Family (VIRTEX & VIRTEX-E)
--
-- Created by: Jean-Louis BRELET / XILINX - VIRTEX Applications
-- Date: September 14, 1999
-- Version: 1.0
--
-- History: 
-- 	1. 
--
--   Disclaimer:  THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY 
--                WHATSOEVER AND XILINX SPECIFICALLY DISCLAIMS ANY 
--                IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR
--                A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT.
--
--  Copyright (c) 1999 Xilinx, Inc.  All rights reserved.
-------------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;

library UNISIM;
use UNISIM.VCOMPONENTS.ALL;

entity TB_CAM_RAMB4 is

end TB_CAM_RAMB4;

architecture TB_CAM_RAMB4_arch of TB_CAM_RAMB4 is
--
-- Components Declarations:
component CAM_RAMB4
    	port (
        	DATA_IN		: in std_logic_vector (7 downto 0);	
        	ADDR		: in std_logic_vector (3 downto 0);
       	WRITE_ENABLE	: in std_logic;
       	ERASE_WRITE	: in std_logic;
       	WRITE_RAM	: in std_logic;	
       	 CLK		: in std_logic;
       	 MATCH_ENABLE	: in std_logic;	
        	MATCH_RST	: in std_logic;	
--        	GLOBAL_RST	: in std_logic;		
        	MATCH		: out std_logic_vector (15 downto 0)
    	);
end component;
--
--
-- Signal Declarations:
--
signal DATA_IN		: std_logic_vector(7 downto 0) ;
signal ADDR		: std_logic_vector(3 downto 0) ; 
signal WRITE_ENABLE	: std_logic;
signal ERASE_WRITE	: std_logic;
signal WRITE_RAM		: std_logic;
signal CLK		: std_logic := '0';
signal MATCH_ENABLE	: std_logic;
signal MATCH_RST		: std_logic; 
-- signal GLOBAL_RST	: std_logic;
signal MATCH		: std_logic_vector(15 downto 0); 
--
type test_record_cam is record
	DATA_IN 		: std_logic_vector(7 downto 0);
	ADDR		: std_logic_vector(3 downto 0) ; 
	WRITE_ENABLE	: std_logic; 
	ERASE_WRITE	: std_logic;
	WRITE_RAM	: std_logic;
	MATCH_ENABLE	: std_logic;
	MATCH_RST	: std_logic; 
	MATCH		: std_logic_vector(15 downto 0); 
end record;
--
type test_array_cam is array(positive range <>) of test_record_cam;
--
constant TEST_PATTERNS : test_array_cam := (
(DATA_IN => "00000000", ADDR => "0000", WRITE_ENABLE => '0', ERASE_WRITE => '0', WRITE_RAM => '0', MATCH_ENABLE => '0', MATCH_RST => '1',  MATCH => "XXXXXXXXXXXXXXXX"),
	-- Synchronous reset
(DATA_IN => "00000000", ADDR => "0000", WRITE_ENABLE => '0', ERASE_WRITE => '0', WRITE_RAM => '0', MATCH_ENABLE => '1', MATCH_RST => '0',  MATCH => "0000000000000000"),
	-- 1- Write Operation DATA_IN at the address ADDR
(DATA_IN => "00000001", ADDR => "0010", WRITE_ENABLE => '1', ERASE_WRITE => '0', WRITE_RAM => '1', MATCH_ENABLE => '0', MATCH_RST => '1',  MATCH => "0000000000000000"),
(DATA_IN => "00000000", ADDR => "0010", WRITE_ENABLE => '1', ERASE_WRITE => '1', WRITE_RAM => '0', MATCH_ENABLE => '0', MATCH_RST => '1',  MATCH => "0000000000000000"),
	-- Dummy clock cycle
(DATA_IN => "00000000", ADDR => "0000", WRITE_ENABLE => '0', ERASE_WRITE => '0', WRITE_RAM => '0', MATCH_ENABLE => '0', MATCH_RST => '1',  MATCH => "0000000000000000"),
	-- 1- Read Operation of the first DATA
(DATA_IN => "00000001", ADDR => "0000", WRITE_ENABLE => '0', ERASE_WRITE => '0', WRITE_RAM => '0', MATCH_ENABLE => '1', MATCH_RST => '1',  MATCH => "0000000000000100"),
(DATA_IN => "00000000", ADDR => "0000", WRITE_ENABLE => '0', ERASE_WRITE => '0', WRITE_RAM => '0', MATCH_ENABLE => '0', MATCH_RST => '1',  MATCH => "0000000000000100"),
	-- 2- Write Operation DATA_IN at the address ADDR
(DATA_IN => "11011111", ADDR => "1100", WRITE_ENABLE => '1', ERASE_WRITE => '0', WRITE_RAM => '1', MATCH_ENABLE => '1', MATCH_RST => '0',  MATCH => "0000000000000000"),
(DATA_IN => "11011111", ADDR => "1100", WRITE_ENABLE => '1', ERASE_WRITE => '1', WRITE_RAM => '0', MATCH_ENABLE => '0', MATCH_RST => '1',  MATCH => "0000000000000000"),
	-- 3- Write Operation DATA_IN at the address ADDR
(DATA_IN => "10100000", ADDR => "1111", WRITE_ENABLE => '1', ERASE_WRITE => '0', WRITE_RAM => '1', MATCH_ENABLE => '0', MATCH_RST => '1',  MATCH => "0000000000000000"),
(DATA_IN => "10100000", ADDR => "1111", WRITE_ENABLE => '1', ERASE_WRITE => '1', WRITE_RAM => '0', MATCH_ENABLE => '0', MATCH_RST => '1',  MATCH => "0000000000000000"),
	-- 4- Write Operation DATA_IN at the address ADDR
(DATA_IN => "01101001", ADDR => "0101", WRITE_ENABLE => '1', ERASE_WRITE => '0', WRITE_RAM => '1', MATCH_ENABLE => '0', MATCH_RST => '1',  MATCH => "0000000000000000"),
(DATA_IN => "00000000", ADDR => "0101", WRITE_ENABLE => '1', ERASE_WRITE => '1', WRITE_RAM => '0', MATCH_ENABLE => '0', MATCH_RST => '1',  MATCH => "0000000000000000"),
	-- 4 & 3 & 2 & non-existing data & 1 read back
(DATA_IN => "01101001", ADDR => "0000", WRITE_ENABLE => '0', ERASE_WRITE => '0', WRITE_RAM => '0', MATCH_ENABLE => '1', MATCH_RST => '1',  MATCH => "0000000000100000"),
(DATA_IN => "10100000", ADDR => "0000", WRITE_ENABLE => '0', ERASE_WRITE => '0', WRITE_RAM => '0', MATCH_ENABLE => '1', MATCH_RST => '1',  MATCH => "1000000000000000"),
(DATA_IN => "11011111", ADDR => "0000", WRITE_ENABLE => '0', ERASE_WRITE => '0', WRITE_RAM => '0', MATCH_ENABLE => '1', MATCH_RST => '1',  MATCH => "0001000000000000"),
(DATA_IN => "01100001", ADDR => "0000", WRITE_ENABLE => '0', ERASE_WRITE => '0', WRITE_RAM => '0', MATCH_ENABLE => '1', MATCH_RST => '1',  MATCH => "0000000000000000"),
(DATA_IN => "00000001", ADDR => "0000", WRITE_ENABLE => '0', ERASE_WRITE => '0', WRITE_RAM => '0', MATCH_ENABLE => '1', MATCH_RST => '1',  MATCH => "0000000000000100"),
	-- 5 Write operation DATA_IN at the address ADDR (same address than the first write)
(DATA_IN => "11111111", ADDR => "0010", WRITE_ENABLE => '1', ERASE_WRITE => '0', WRITE_RAM => '1', MATCH_ENABLE => '0', MATCH_RST => '1',  MATCH => "0000000000000100"),
(DATA_IN => "11111111", ADDR => "0010", WRITE_ENABLE => '1', ERASE_WRITE => '1', WRITE_RAM => '0', MATCH_ENABLE => '0', MATCH_RST => '1',  MATCH => "0000000000000100"),
	-- 1 read back the erase n 1
(DATA_IN => "00000001", ADDR => "0000", WRITE_ENABLE => '0', ERASE_WRITE => '0', WRITE_RAM => '0', MATCH_ENABLE => '1', MATCH_RST => '1',  MATCH => "0000000000000000"),
	-- 6- Write operation DATA_IN (same than n 1) at the address ADRR
(DATA_IN => "00000001", ADDR => "0011", WRITE_ENABLE => '1', ERASE_WRITE => '0', WRITE_RAM => '1', MATCH_ENABLE => '0', MATCH_RST => '1',  MATCH => "0000000000000000"),
(DATA_IN => "00000001", ADDR => "0011", WRITE_ENABLE => '1', ERASE_WRITE => '1', WRITE_RAM => '0', MATCH_ENABLE => '0', MATCH_RST => '1',  MATCH => "0000000000000000"),
	-- 5 & 6 & Non-existing data read back
(DATA_IN => "11111111", ADDR => "0000", WRITE_ENABLE => '0', ERASE_WRITE => '0', WRITE_RAM => '0', MATCH_ENABLE => '1', MATCH_RST => '1',  MATCH => "0000000000000100"),
(DATA_IN => "10000001", ADDR => "0000", WRITE_ENABLE => '0', ERASE_WRITE => '0', WRITE_RAM => '0', MATCH_ENABLE => '1', MATCH_RST => '1',  MATCH => "0000000000000000"),
(DATA_IN => "00000001", ADDR => "0000", WRITE_ENABLE => '0', ERASE_WRITE => '0', WRITE_RAM => '0', MATCH_ENABLE => '1', MATCH_RST => '1',  MATCH => "0000000000001000"),
	-- Dummy clock cycle /Test MATCH Reset
(DATA_IN => "00000000", ADDR => "0000", WRITE_ENABLE => '0', ERASE_WRITE => '0', WRITE_RAM => '0', MATCH_ENABLE => '1', MATCH_RST => '0',  MATCH => "0000000000000000"),
	-- 7- Write operation DATA_IN at the address ADDR "0000"
(DATA_IN => "00000001", ADDR => "0000", WRITE_ENABLE => '1', ERASE_WRITE => '0', WRITE_RAM => '1', MATCH_ENABLE => '0', MATCH_RST => '1',  MATCH => "0000000000000000"),
(DATA_IN => "00000001", ADDR => "0000", WRITE_ENABLE => '1', ERASE_WRITE => '1', WRITE_RAM => '0', MATCH_ENABLE => '0', MATCH_RST => '1',  MATCH => "0000000000000000"),
	-- 8- Write operation DATA_IN (same than n 4) at the address ADDR
(DATA_IN => "11000010", ADDR => "0101", WRITE_ENABLE => '1', ERASE_WRITE => '0', WRITE_RAM => '1', MATCH_ENABLE => '0', MATCH_RST => '1',  MATCH => "0000000000000000"),
(DATA_IN => "11000010", ADDR => "0101", WRITE_ENABLE => '1', ERASE_WRITE => '1', WRITE_RAM => '0', MATCH_ENABLE => '0', MATCH_RST => '1',  MATCH => "0000000000000000"),	
	-- Multi-matched (n 6 & n 7) & 8 & 5 read back
(DATA_IN => "00000001", ADDR => "0000", WRITE_ENABLE => '0', ERASE_WRITE => '0', WRITE_RAM => '0', MATCH_ENABLE => '1', MATCH_RST => '1',  MATCH => "0000000000001001"),
(DATA_IN => "11000010", ADDR => "0000", WRITE_ENABLE => '0', ERASE_WRITE => '0', WRITE_RAM => '0', MATCH_ENABLE => '1', MATCH_RST => '1',  MATCH => "0000000000100000"),
(DATA_IN => "11111111", ADDR => "0000", WRITE_ENABLE => '0', ERASE_WRITE => '0', WRITE_RAM => '0', MATCH_ENABLE => '1', MATCH_RST => '1',  MATCH => "0000000000000100"),
	-- Dummy clock cycles
(DATA_IN => "00000000", ADDR => "0000", WRITE_ENABLE => '0', ERASE_WRITE => '0', WRITE_RAM => '0', MATCH_ENABLE => '0', MATCH_RST => '1',  MATCH => "0000000000000100"),
	-- 9- Write operation DATA_IN (same than n 4 & n 8) at the address ADDR
(DATA_IN => "11000010", ADDR => "1100", WRITE_ENABLE => '1', ERASE_WRITE => '0', WRITE_RAM => '1', MATCH_ENABLE => '0', MATCH_RST => '1',  MATCH => "0000000000000100"),
(DATA_IN => "11000010", ADDR => "1100", WRITE_ENABLE => '1', ERASE_WRITE => '1', WRITE_RAM => '0', MATCH_ENABLE => '0', MATCH_RST => '1',  MATCH => "0000000000000100"),
	-- 10- Write operation DATA_IN (same than n 4 & n 8) at the address ADDR
(DATA_IN => "11000010", ADDR => "0111", WRITE_ENABLE => '1', ERASE_WRITE => '0', WRITE_RAM => '1', MATCH_ENABLE => '0', MATCH_RST => '1',  MATCH => "0000000000000100"),
(DATA_IN => "11000010", ADDR => "0111", WRITE_ENABLE => '1', ERASE_WRITE => '1', WRITE_RAM => '0', MATCH_ENABLE => '0', MATCH_RST => '1',  MATCH => "0000000000000100"),	
	-- Read Multi-matches (n 8 & n 9 & n 10) read back
(DATA_IN => "00000001", ADDR => "0000", WRITE_ENABLE => '0', ERASE_WRITE => '0', WRITE_RAM => '0', MATCH_ENABLE => '1', MATCH_RST => '1',  MATCH => "0000000000001001"),
(DATA_IN => "11000010", ADDR => "0000", WRITE_ENABLE => '0', ERASE_WRITE => '0', WRITE_RAM => '0', MATCH_ENABLE => '1', MATCH_RST => '1',  MATCH => "0001000010100000"),
	-- Synchronous reset
(DATA_IN => "00000000", ADDR => "0000", WRITE_ENABLE => '0', ERASE_WRITE => '0', WRITE_RAM => '0', MATCH_ENABLE => '1', MATCH_RST => '0',  MATCH => "0000000000000000"),
	-- Dummy clock cycle
(DATA_IN => "00000000", ADDR => "0000", WRITE_ENABLE => '0', ERASE_WRITE => '0', WRITE_RAM => '0', MATCH_ENABLE => '0', MATCH_RST => '1',  MATCH => "0000000000000000"),
(DATA_IN => "00000000", ADDR => "0000", WRITE_ENABLE => '0', ERASE_WRITE => '0', WRITE_RAM => '0', MATCH_ENABLE => '0', MATCH_RST => '1',  MATCH => "0000000000000000")
);
--
--
begin
-- CAM_RAMB4 instantiation 
UUT : CAM_RAMB4
	port map (
	DATA_IN => DATA_IN,
       	 ADDR => ADDR,
       	 WRITE_ENABLE => WRITE_ENABLE,
       	 ERASE_WRITE => ERASE_WRITE,
       	 WRITE_RAM => WRITE_RAM,
	CLK => CLK,
	MATCH_ENABLE => MATCH_ENABLE,	
	MATCH_RST => MATCH_RST,
--        	GLOBAL_RST => GLOBAL_RST,		
       	 MATCH => MATCH
	);
--
CLK <= not CLK after 5 ns;
--
-- Global Reset
--GLOBAL_RESET: process
--begin
--	GLOBAL_RST <= '0';
--	wait for 8 ns;
--	GLOBAL_RST <= '1';
--	wait for 15 ns;
--	GLOBAL_RST <= '0';
--	wait;
--end process GLOBAL_RESET;

-- Stimulus
TEST_CAM: process
variable VECTOR : test_record_cam;
variable ERROR : boolean := false;
begin

	for i in TEST_PATTERNS'range loop
	 	VECTOR := TEST_PATTERNS(i);

		-- Apply the stimulus
		DATA_IN <= VECTOR.DATA_IN;
		ADDR <= VECTOR.ADDR;
		WRITE_ENABLE <= VECTOR.WRITE_ENABLE;
		ERASE_WRITE <= VECTOR.ERASE_WRITE;
		WRITE_RAM <= VECTOR.WRITE_RAM;
		MATCH_ENABLE <= VECTOR.MATCH_ENABLE;
		MATCH_RST <= VECTOR.MATCH_RST;
--
--		Comparison to the expected results
--
	    -- wait for the outputs to settle
	    wait for 10 ns;
end loop;
--
end process TEST_CAM;
--		
end TB_CAM_RAMB4_arch;