📄 full_adder.tan.rpt
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Classic Timing Analyzer report for full_adder
Sun Nov 30 13:13:45 2008
Quartus II Version 8.0 Build 215 05/29/2008 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. tpd
5. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-------+---------------+-------------+-----------+------+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+-------------+-----------+------+------------+----------+--------------+
; Worst-case tpd ; N/A ; None ; 17.372 ns ; OPERATION ; S[3] ; -- ; -- ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+-------------+-----------+------+------------+----------+--------------+
+--------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EP1C6Q240C8 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Default hold multicycle ; Same as Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; On ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
; Use TimeQuest Timing Analyzer ; Off ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
; Perform Multicorner Analysis ; Off ; ; ; ;
; Reports the worst-case path for each clock domain and analysis ; Off ; ; ; ;
; Removes common clock path pessimism (CCPP) during slack computation ; Off ; ; ; ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+
+----------------------------------------------------------------+
; tpd ;
+-------+-------------------+-----------------+-----------+------+
; Slack ; Required P2P Time ; Actual P2P Time ; From ; To ;
+-------+-------------------+-----------------+-----------+------+
; N/A ; None ; 17.372 ns ; OPERATION ; S[3] ;
; N/A ; None ; 16.731 ns ; A[2] ; S[3] ;
; N/A ; None ; 16.135 ns ; A[0] ; S[3] ;
; N/A ; None ; 16.019 ns ; OPERATION ; SIGN ;
; N/A ; None ; 15.997 ns ; Cin ; S[3] ;
; N/A ; None ; 15.378 ns ; A[2] ; SIGN ;
; N/A ; None ; 14.883 ns ; B[0] ; S[3] ;
; N/A ; None ; 14.790 ns ; B[1] ; S[3] ;
; N/A ; None ; 14.782 ns ; A[0] ; SIGN ;
; N/A ; None ; 14.727 ns ; OPERATION ; Co ;
; N/A ; None ; 14.702 ns ; A[1] ; S[3] ;
; N/A ; None ; 14.644 ns ; Cin ; SIGN ;
; N/A ; None ; 14.289 ns ; B[2] ; S[3] ;
; N/A ; None ; 14.086 ns ; A[2] ; Co ;
; N/A ; None ; 14.072 ns ; OPERATION ; S[2] ;
; N/A ; None ; 13.822 ns ; OPERATION ; S[1] ;
; N/A ; None ; 13.530 ns ; B[0] ; SIGN ;
; N/A ; None ; 13.490 ns ; A[0] ; Co ;
; N/A ; None ; 13.444 ns ; OPERATION ; S[0] ;
; N/A ; None ; 13.437 ns ; B[1] ; SIGN ;
; N/A ; None ; 13.427 ns ; A[2] ; S[2] ;
; N/A ; None ; 13.352 ns ; Cin ; Co ;
; N/A ; None ; 13.349 ns ; A[1] ; SIGN ;
; N/A ; None ; 12.936 ns ; B[2] ; SIGN ;
; N/A ; None ; 12.860 ns ; B[3] ; S[3] ;
; N/A ; None ; 12.835 ns ; A[0] ; S[2] ;
; N/A ; None ; 12.712 ns ; A[3] ; S[3] ;
; N/A ; None ; 12.697 ns ; Cin ; S[2] ;
; N/A ; None ; 12.585 ns ; A[0] ; S[1] ;
; N/A ; None ; 12.447 ns ; Cin ; S[1] ;
; N/A ; None ; 12.238 ns ; B[0] ; Co ;
; N/A ; None ; 12.213 ns ; A[0] ; S[0] ;
; N/A ; None ; 12.145 ns ; B[1] ; Co ;
; N/A ; None ; 12.071 ns ; Cin ; S[0] ;
; N/A ; None ; 12.057 ns ; A[1] ; Co ;
; N/A ; None ; 11.644 ns ; B[2] ; Co ;
; N/A ; None ; 11.583 ns ; B[0] ; S[2] ;
; N/A ; None ; 11.506 ns ; B[3] ; SIGN ;
; N/A ; None ; 11.490 ns ; B[1] ; S[2] ;
; N/A ; None ; 11.402 ns ; A[1] ; S[2] ;
; N/A ; None ; 11.361 ns ; A[3] ; SIGN ;
; N/A ; None ; 11.333 ns ; B[0] ; S[1] ;
; N/A ; None ; 11.240 ns ; B[1] ; S[1] ;
; N/A ; None ; 11.156 ns ; A[1] ; S[1] ;
; N/A ; None ; 10.986 ns ; B[2] ; S[2] ;
; N/A ; None ; 10.957 ns ; B[0] ; S[0] ;
; N/A ; None ; 10.212 ns ; B[3] ; Co ;
; N/A ; None ; 10.070 ns ; A[3] ; Co ;
+-------+-------------------+-----------------+-----------+------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
Info: Version 8.0 Build 215 05/29/2008 SJ Full Version
Info: Processing started: Sun Nov 30 13:13:44 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off full_adder -c full_adder --timing_analysis_only
Info: Longest tpd from source pin "OPERATION" to destination pin "S[3]" is 17.372 ns
Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_98; Fanout = 9; PIN Node = 'OPERATION'
Info: 2: + IC(7.402 ns) + CELL(0.114 ns) = 8.991 ns; Loc. = LC_X1_Y7_N3; Fanout = 2; COMB Node = 'full_adder1:inst4|inst5~1'
Info: 3: + IC(0.446 ns) + CELL(0.114 ns) = 9.551 ns; Loc. = LC_X1_Y7_N5; Fanout = 2; COMB Node = 'full_adder1:inst3|inst5~1'
Info: 4: + IC(0.423 ns) + CELL(0.442 ns) = 10.416 ns; Loc. = LC_X1_Y7_N9; Fanout = 3; COMB Node = 'full_adder1:inst2|inst5~1'
Info: 5: + IC(0.461 ns) + CELL(0.292 ns) = 11.169 ns; Loc. = LC_X1_Y7_N4; Fanout = 1; COMB Node = 'full_adder1:inst|inst3~17'
Info: 6: + IC(4.079 ns) + CELL(2.124 ns) = 17.372 ns; Loc. = PIN_138; Fanout = 0; PIN Node = 'S[3]'
Info: Total cell delay = 4.561 ns ( 26.25 % )
Info: Total interconnect delay = 12.811 ns ( 73.75 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 0 warnings
Info: Peak virtual memory: 120 megabytes
Info: Processing ended: Sun Nov 30 13:13:45 2008
Info: Elapsed time: 00:00:01
Info: Total CPU time (on all processors): 00:00:01
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