readme.txt

Xilinx APP Generators Using the SRL Macro

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Readme File for: XAPP211 - PN Generator Using the Virtex SRL Macro

Created: 1/31/00 MPG
Revised: 1/31/00 MPG

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File Contents
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This zip file contains the following files:

pn_gen_srl_test.v    - Top-level, self-checking test bench that instantiates the pn generator. This verilog test bench works with both (Verilog and VHDL) versions of the design. ModelSim EE Plus/5.2e will support mixed HDL simulations.

iq_pn_gen.v          - Verilog RTL version of pn generator code.

iq_pn_gen.vhd        - VHDL RTL version of pn generator code.

pni_gold.dat         - "Golden" I channel data used by the test bench to compare against actual
                       pn sequence generated by the design.

pnq_gold.dat         - "Golden" Q channel data used by the test bench to compare against actual
                       pn sequence generated by the design.
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Synthesis:
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Comments are provided in both the verilog (iq_pn_gen.v) and VHDL (iq_pn_gen.vhd) versions of 
the PN generator RTL code that indicate what parameters are available to customize the implementation.  
In the verilog version, the number of taps are fixed however the tap points and LFSR width are 
parameratizable.  In the VHDL version, the number of taps, tap points, and LFSR width are all 
parameratizable.

All three synthesis vendors, Synplify 2.2.2a, FPGA Express 3.3, and Leonardo v1999.1g were used
to implement the LFSRs very efficiently utilizing the Virtex Shift Register LUT (SRL16E).  
The verilog code version provides a `define compiler directive that can be 
used to steer the code to infer Flip-flops instead of SRL16E elements.  This can be useful 
allowing the code to be written such that it takes advantage of the Virtex SRL16Es when 
targetting Virtex, but also allows for easy portability to other non-Virtex technologies 
(ie, ASICs).
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Simulation:
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Using ModelSim, compile the pn_gen_srl_test.v and either the verilog version (iq_pn_gen.v)
or VHDL version (iq_pn_gen.vhd) of the pn generator.  The clock period is set in the test 
bench for 10ns.  The example LFSRs in the code have a length of 17 bits wide therefore they
will produce a pn sequence 2^^17 - 1 bits long (before repeating).  Run the simulation for 
approximately 1.32 ms to simulate the entire sequence.  (At a 10 ns clock period, the entire
sequence will take 1,310,710 ns.)

The test bench is self-checking and will compare the output of the I channel LFSR and Q channel
LFSR with "golden" data from the pni_gold.dat and pnq_gold.dat files, respectively.  Each bit 
comparison is reported in the command window showing the simulation time, the golden bit value, 
and the actual bit value.  If there's a mismatch between the two bits, the simluation will stop.  

The test bench will also produce two files containing the actual bits generated.  Bits generated
from the I channel LFSR will be written in a file called pni_testout.dat, and bits generated
from the Q channel LFSR will be written in a file called pnq_testout.dat.
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