anal.out

VHDL的实例加解说,对初学习者用处很大的!

E:/vhdl_tools/100Examples/1_ADDER/1_ADDER.VHD:
		 pout <= in1+in2;
		            ^
**Error: E:/vhdl_tools/100Examples/1_ADDER/1_ADDER.VHD  line 15
	Type mismatch on left and/or right operand of binary operator. (VSS-523)