display.tan.rpt

实现交通灯控制器的vhdl编程

; N/A           ; None        ; -0.309 ns ; qin[1] ; display[1]~reg0 ; clock    ;
; N/A           ; None        ; -0.309 ns ; qin[1] ; display[2]~reg0 ; clock    ;
; N/A           ; None        ; -3.442 ns ; qin[3] ; display[2]~reg0 ; clock    ;
; N/A           ; None        ; -3.443 ns ; qin[3] ; display[1]~reg0 ; clock    ;
; N/A           ; None        ; -3.643 ns ; qin[2] ; display[2]~reg0 ; clock    ;
; N/A           ; None        ; -3.647 ns ; qin[2] ; display[1]~reg0 ; clock    ;
; N/A           ; None        ; -3.770 ns ; qin[2] ; display[5]~reg0 ; clock    ;
; N/A           ; None        ; -3.800 ns ; qin[3] ; display[5]~reg0 ; clock    ;
; N/A           ; None        ; -3.808 ns ; qin[2] ; display[6]~reg0 ; clock    ;
; N/A           ; None        ; -3.837 ns ; qin[3] ; display[6]~reg0 ; clock    ;
; N/A           ; None        ; -3.900 ns ; qin[2] ; display[4]~reg0 ; clock    ;
; N/A           ; None        ; -3.906 ns ; qin[2] ; display[0]~reg0 ; clock    ;
; N/A           ; None        ; -3.907 ns ; qin[2] ; display[3]~reg0 ; clock    ;
; N/A           ; None        ; -3.930 ns ; qin[3] ; display[4]~reg0 ; clock    ;
; N/A           ; None        ; -3.935 ns ; qin[3] ; display[3]~reg0 ; clock    ;
; N/A           ; None        ; -3.936 ns ; qin[3] ; display[0]~reg0 ; clock    ;
; N/A           ; None        ; -4.133 ns ; flash  ; timeout[4]      ; clock    ;
; N/A           ; None        ; -4.133 ns ; flash  ; timeout[2]      ; clock    ;
; N/A           ; None        ; -4.133 ns ; flash  ; timeout[3]      ; clock    ;
; N/A           ; None        ; -4.133 ns ; flash  ; timeout[0]      ; clock    ;
; N/A           ; None        ; -4.133 ns ; flash  ; timeout[1]      ; clock    ;
+---------------+-------------+-----------+--------+-----------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Thu Oct 16 09:47:22 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off display -c display --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clock" is an undefined clock
Info: Clock "clock" Internal fmax is restricted to 420.17 MHz between source register "timeout[3]" and destination register "timeout[4]"
    Info: fmax restricted to clock pin edge rate 2.38 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 1.905 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X23_Y35_N21; Fanout = 10; REG Node = 'timeout[3]'
            Info: 2: + IC(0.336 ns) + CELL(0.438 ns) = 0.774 ns; Loc. = LCCOMB_X23_Y35_N6; Fanout = 1; COMB Node = 'timeout[4]~136'
            Info: 3: + IC(0.240 ns) + CELL(0.150 ns) = 1.164 ns; Loc. = LCCOMB_X23_Y35_N24; Fanout = 5; COMB Node = 'timeout[4]~137'
            Info: 4: + IC(0.231 ns) + CELL(0.510 ns) = 1.905 ns; Loc. = LCFF_X23_Y35_N23; Fanout = 9; REG Node = 'timeout[4]'
            Info: Total cell delay = 1.098 ns ( 57.64 % )
            Info: Total interconnect delay = 0.807 ns ( 42.36 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clock" to destination register is 2.691 ns
                Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clock'
                Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 12; COMB Node = 'clock~clkctrl'
                Info: 3: + IC(1.037 ns) + CELL(0.537 ns) = 2.691 ns; Loc. = LCFF_X23_Y35_N23; Fanout = 9; REG Node = 'timeout[4]'
                Info: Total cell delay = 1.536 ns ( 57.08 % )
                Info: Total interconnect delay = 1.155 ns ( 42.92 % )
            Info: - Longest clock path from clock "clock" to source register is 2.691 ns
                Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clock'
                Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 12; COMB Node = 'clock~clkctrl'
                Info: 3: + IC(1.037 ns) + CELL(0.537 ns) = 2.691 ns; Loc. = LCFF_X23_Y35_N21; Fanout = 10; REG Node = 'timeout[3]'
                Info: Total cell delay = 1.536 ns ( 57.08 % )
                Info: Total interconnect delay = 1.155 ns ( 42.92 % )
        Info: + Micro clock to output delay of source is 0.250 ns
        Info: + Micro setup delay of destination is -0.036 ns
Info: tsu for register "timeout[4]" (data pin = "flash", clock pin = "clock") is 4.363 ns
    Info: + Longest pin to register delay is 7.090 ns
        Info: 1: + IC(0.000 ns) + CELL(0.880 ns) = 0.880 ns; Loc. = PIN_J10; Fanout = 1; PIN Node = 'flash'
        Info: 2: + IC(5.050 ns) + CELL(0.419 ns) = 6.349 ns; Loc. = LCCOMB_X23_Y35_N24; Fanout = 5; COMB Node = 'timeout[4]~137'
        Info: 3: + IC(0.231 ns) + CELL(0.510 ns) = 7.090 ns; Loc. = LCFF_X23_Y35_N23; Fanout = 9; REG Node = 'timeout[4]'
        Info: Total cell delay = 1.809 ns ( 25.51 % )
        Info: Total interconnect delay = 5.281 ns ( 74.49 % )
    Info: + Micro setup delay of destination is -0.036 ns
    Info: - Shortest clock path from clock "clock" to destination register is 2.691 ns
        Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clock'
        Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 12; COMB Node = 'clock~clkctrl'
        Info: 3: + IC(1.037 ns) + CELL(0.537 ns) = 2.691 ns; Loc. = LCFF_X23_Y35_N23; Fanout = 9; REG Node = 'timeout[4]'
        Info: Total cell delay = 1.536 ns ( 57.08 % )
        Info: Total interconnect delay = 1.155 ns ( 42.92 % )
Info: tco from clock "clock" to destination pin "display[6]" through register "display[6]~reg0" is 6.846 ns
    Info: + Longest clock path from clock "clock" to source register is 2.691 ns
        Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clock'
        Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 12; COMB Node = 'clock~clkctrl'
        Info: 3: + IC(1.037 ns) + CELL(0.537 ns) = 2.691 ns; Loc. = LCFF_X23_Y35_N3; Fanout = 1; REG Node = 'display[6]~reg0'
        Info: Total cell delay = 1.536 ns ( 57.08 % )
        Info: Total interconnect delay = 1.155 ns ( 42.92 % )
    Info: + Micro clock to output delay of source is 0.250 ns
    Info: + Longest register to pin delay is 3.905 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X23_Y35_N3; Fanout = 1; REG Node = 'display[6]~reg0'
        Info: 2: + IC(1.087 ns) + CELL(2.818 ns) = 3.905 ns; Loc. = PIN_J11; Fanout = 0; PIN Node = 'display[6]'
        Info: Total cell delay = 2.818 ns ( 72.16 % )
        Info: Total interconnect delay = 1.087 ns ( 27.84 % )
Info: th for register "display[2]~reg0" (data pin = "qin[0]", clock pin = "clock") is 0.222 ns
    Info: + Longest clock path from clock "clock" to destination register is 2.691 ns
        Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clock'
        Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 12; COMB Node = 'clock~clkctrl'
        Info: 3: + IC(1.037 ns) + CELL(0.537 ns) = 2.691 ns; Loc. = LCFF_X23_Y35_N13; Fanout = 1; REG Node = 'display[2]~reg0'
        Info: Total cell delay = 1.536 ns ( 57.08 % )
        Info: Total interconnect delay = 1.155 ns ( 42.92 % )
    Info: + Micro hold delay of destination is 0.266 ns
    Info: - Shortest pin to register delay is 2.735 ns
        Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_C13; Fanout = 7; PIN Node = 'qin[0]'
        Info: 2: + IC(1.130 ns) + CELL(0.150 ns) = 2.259 ns; Loc. = LCCOMB_X23_Y35_N26; Fanout = 1; COMB Node = 'Mux4~26'
        Info: 3: + IC(0.243 ns) + CELL(0.149 ns) = 2.651 ns; Loc. = LCCOMB_X23_Y35_N12; Fanout = 1; COMB Node = 'display~72'
        Info: 4: + IC(0.000 ns) + CELL(0.084 ns) = 2.735 ns; Loc. = LCFF_X23_Y35_N13; Fanout = 1; REG Node = 'display[2]~reg0'
        Info: Total cell delay = 1.362 ns ( 49.80 % )
        Info: Total interconnect delay = 1.373 ns ( 50.20 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Thu Oct 16 09:47:22 2008
    Info: Elapsed time: 00:00:01