display.tan.qmsg

实现交通灯控制器的vhdl编程

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clock register register timeout\[3\] timeout\[4\] 420.17 MHz Internal " "Info: Clock \"clock\" Internal fmax is restricted to 420.17 MHz between source register \"timeout\[3\]\" and destination register \"timeout\[4\]\"" { { "Info" "ITDB_CLOCK_RATE" "clock 2.38 ns " "Info: fmax restricted to clock pin edge rate 2.38 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.905 ns + Longest register register " "Info: + Longest register to register delay is 1.905 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns timeout\[3\] 1 REG LCFF_X23_Y35_N21 10 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X23_Y35_N21; Fanout = 10; REG Node = 'timeout\[3\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { timeout[3] } "NODE_NAME" } } { "display.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/display/display.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.336 ns) + CELL(0.438 ns) 0.774 ns timeout\[4\]~136 2 COMB LCCOMB_X23_Y35_N6 1 " "Info: 2: + IC(0.336 ns) + CELL(0.438 ns) = 0.774 ns; Loc. = LCCOMB_X23_Y35_N6; Fanout = 1; COMB Node = 'timeout\[4\]~136'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.774 ns" { timeout[3] timeout[4]~136 } "NODE_NAME" } } { "display.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/display/display.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.240 ns) + CELL(0.150 ns) 1.164 ns timeout\[4\]~137 3 COMB LCCOMB_X23_Y35_N24 5 " "Info: 3: + IC(0.240 ns) + CELL(0.150 ns) = 1.164 ns; Loc. = LCCOMB_X23_Y35_N24; Fanout = 5; COMB Node = 'timeout\[4\]~137'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.390 ns" { timeout[4]~136 timeout[4]~137 } "NODE_NAME" } } { "display.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/display/display.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.231 ns) + CELL(0.510 ns) 1.905 ns timeout\[4\] 4 REG LCFF_X23_Y35_N23 9 " "Info: 4: + IC(0.231 ns) + CELL(0.510 ns) = 1.905 ns; Loc. = LCFF_X23_Y35_N23; Fanout = 9; REG Node = 'timeout\[4\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.741 ns" { timeout[4]~137 timeout[4] } "NODE_NAME" } } { "display.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/display/display.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.098 ns ( 57.64 % ) " "Info: Total cell delay = 1.098 ns ( 57.64 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.807 ns ( 42.36 % ) " "Info: Total interconnect delay = 0.807 ns ( 42.36 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.905 ns" { timeout[3] timeout[4]~136 timeout[4]~137 timeout[4] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "1.905 ns" { timeout[3] timeout[4]~136 timeout[4]~137 timeout[4] } { 0.000ns 0.336ns 0.240ns 0.231ns } { 0.000ns 0.438ns 0.150ns 0.510ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 2.691 ns + Shortest register " "Info: + Shortest clock path from clock \"clock\" to destination register is 2.691 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clock 1 CLK PIN_P2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clock'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "display.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/display/display.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns clock~clkctrl 2 COMB CLKCTRL_G3 12 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 12; COMB Node = 'clock~clkctrl'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.118 ns" { clock clock~clkctrl } "NODE_NAME" } } { "display.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/display/display.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.037 ns) + CELL(0.537 ns) 2.691 ns timeout\[4\] 3 REG LCFF_X23_Y35_N23 9 " "Info: 3: + IC(1.037 ns) + CELL(0.537 ns) = 2.691 ns; Loc. = LCFF_X23_Y35_N23; Fanout = 9; REG Node = 'timeout\[4\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.574 ns" { clock~clkctrl timeout[4] } "NODE_NAME" } } { "display.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/display/display.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.08 % ) " "Info: Total cell delay = 1.536 ns ( 57.08 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.155 ns ( 42.92 % ) " "Info: Total interconnect delay = 1.155 ns ( 42.92 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.691 ns" { clock clock~clkctrl timeout[4] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.691 ns" { clock clock~combout clock~clkctrl timeout[4] } { 0.000ns 0.000ns 0.118ns 1.037ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 2.691 ns - Longest register " "Info: - Longest clock path from clock \"clock\" to source register is 2.691 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clock 1 CLK PIN_P2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clock'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "display.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/display/display.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns clock~clkctrl 2 COMB CLKCTRL_G3 12 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 12; COMB Node = 'clock~clkctrl'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.118 ns" { clock clock~clkctrl } "NODE_NAME" } } { "display.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/display/display.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.037 ns) + CELL(0.537 ns) 2.691 ns timeout\[3\] 3 REG LCFF_X23_Y35_N21 10 " "Info: 3: + IC(1.037 ns) + CELL(0.537 ns) = 2.691 ns; Loc. = LCFF_X23_Y35_N21; Fanout = 10; REG Node = 'timeout\[3\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.574 ns" { clock~clkctrl timeout[3] } "NODE_NAME" } } { "display.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/display/display.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.08 % ) " "Info: Total cell delay = 1.536 ns ( 57.08 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.155 ns ( 42.92 % ) " "Info: Total interconnect delay = 1.155 ns ( 42.92 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.691 ns" { clock clock~clkctrl timeout[3] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.691 ns" { clock clock~combout clock~clkctrl timeout[3] } { 0.000ns 0.000ns 0.118ns 1.037ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.691 ns" { clock clock~clkctrl timeout[4] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.691 ns" { clock clock~combout clock~clkctrl timeout[4] } { 0.000ns 0.000ns 0.118ns 1.037ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.691 ns" { clock clock~clkctrl timeout[3] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.691 ns" { clock clock~combout clock~clkctrl timeout[3] } { 0.000ns 0.000ns 0.118ns 1.037ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "display.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/display/display.vhd" 15 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" {  } { { "display.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/display/display.vhd" 15 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.905 ns" { timeout[3] timeout[4]~136 timeout[4]~137 timeout[4] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "1.905 ns" { timeout[3] timeout[4]~136 timeout[4]~137 timeout[4] } { 0.000ns 0.336ns 0.240ns 0.231ns } { 0.000ns 0.438ns 0.150ns 0.510ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.691 ns" { clock clock~clkctrl timeout[4] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.691 ns" { clock clock~combout clock~clkctrl timeout[4] } { 0.000ns 0.000ns 0.118ns 1.037ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.691 ns" { clock clock~clkctrl timeout[3] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.691 ns" { clock clock~combout clock~clkctrl timeout[3] } { 0.000ns 0.000ns 0.118ns 1.037ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } }  } 0 0 "fmax restricted to %1!s! pin edge rate %2!s!. Expand message to see actual delay path." 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { timeout[4] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { timeout[4] } {  } {  } } } { "display.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/display/display.vhd" 15 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_TSU_RESULT" "timeout\[4\] flash clock 4.363 ns register " "Info: tsu for register \"timeout\[4\]\" (data pin = \"flash\", clock pin = \"clock\") is 4.363 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.090 ns + Longest pin register " "Info: + Longest pin to register delay is 7.090 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.880 ns) 0.880 ns flash 1 PIN PIN_J10 1 " "Info: 1: + IC(0.000 ns) + CELL(0.880 ns) = 0.880 ns; Loc. = PIN_J10; Fanout = 1; PIN Node = 'flash'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { flash } "NODE_NAME" } } { "display.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/display/display.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.050 ns) + CELL(0.419 ns) 6.349 ns timeout\[4\]~137 2 COMB LCCOMB_X23_Y35_N24 5 " "Info: 2: + IC(5.050 ns) + CELL(0.419 ns) = 6.349 ns; Loc. = LCCOMB_X23_Y35_N24; Fanout = 5; COMB Node = 'timeout\[4\]~137'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.469 ns" { flash timeout[4]~137 } "NODE_NAME" } } { "display.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/display/display.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.231 ns) + CELL(0.510 ns) 7.090 ns timeout\[4\] 3 REG LCFF_X23_Y35_N23 9 " "Info: 3: + IC(0.231 ns) + CELL(0.510 ns) = 7.090 ns; Loc. = LCFF_X23_Y35_N23; Fanout = 9; REG Node = 'timeout\[4\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.741 ns" { timeout[4]~137 timeout[4] } "NODE_NAME" } } { "display.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/display/display.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.809 ns ( 25.51 % ) " "Info: Total cell delay = 1.809 ns ( 25.51 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.281 ns ( 74.49 % ) " "Info: Total interconnect delay = 5.281 ns ( 74.49 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.090 ns" { flash timeout[4]~137 timeout[4] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "7.090 ns" { flash flash~combout timeout[4]~137 timeout[4] } { 0.000ns 0.000ns 5.050ns 0.231ns } { 0.000ns 0.880ns 0.419ns 0.510ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" {  } { { "display.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/display/display.vhd" 15 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 2.691 ns - Shortest register " "Info: - Shortest clock path from clock \"clock\" to destination register is 2.691 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clock 1 CLK PIN_P2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clock'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "display.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/display/display.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns clock~clkctrl 2 COMB CLKCTRL_G3 12 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 12; COMB Node = 'clock~clkctrl'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.118 ns" { clock clock~clkctrl } "NODE_NAME" } } { "display.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/display/display.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.037 ns) + CELL(0.537 ns) 2.691 ns timeout\[4\] 3 REG LCFF_X23_Y35_N23 9 " "Info: 3: + IC(1.037 ns) + CELL(0.537 ns) = 2.691 ns; Loc. = LCFF_X23_Y35_N23; Fanout = 9; REG Node = 'timeout\[4\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.574 ns" { clock~clkctrl timeout[4] } "NODE_NAME" } } { "display.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/display/display.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.08 % ) " "Info: Total cell delay = 1.536 ns ( 57.08 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.155 ns ( 42.92 % ) " "Info: Total interconnect delay = 1.155 ns ( 42.92 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.691 ns" { clock clock~clkctrl timeout[4] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.691 ns" { clock clock~combout clock~clkctrl timeout[4] } { 0.000ns 0.000ns 0.118ns 1.037ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.090 ns" { flash timeout[4]~137 timeout[4] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "7.090 ns" { flash flash~combout timeout[4]~137 timeout[4] } { 0.000ns 0.000ns 5.050ns 0.231ns } { 0.000ns 0.880ns 0.419ns 0.510ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.691 ns" { clock clock~clkctrl timeout[4] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.691 ns" { clock clock~combout clock~clkctrl timeout[4] } { 0.000ns 0.000ns 0.118ns 1.037ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clock display\[6\] display\[6\]~reg0 6.846 ns register " "Info: tco from clock \"clock\" to destination pin \"display\[6\]\" through register \"display\[6\]~reg0\" is 6.846 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 2.691 ns + Longest register " "Info: + Longest clock path from clock \"clock\" to source register is 2.691 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clock 1 CLK PIN_P2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clock'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "display.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/display/display.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns clock~clkctrl 2 COMB CLKCTRL_G3 12 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 12; COMB Node = 'clock~clkctrl'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.118 ns" { clock clock~clkctrl } "NODE_NAME" } } { "display.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/display/display.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.037 ns) + CELL(0.537 ns) 2.691 ns display\[6\]~reg0 3 REG LCFF_X23_Y35_N3 1 " "Info: 3: + IC(1.037 ns) + CELL(0.537 ns) = 2.691 ns; Loc. = LCFF_X23_Y35_N3; Fanout = 1; REG Node = 'display\[6\]~reg0'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.574 ns" { clock~clkctrl display[6]~reg0 } "NODE_NAME" } } { "display.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/display/display.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.08 % ) " "Info: Total cell delay = 1.536 ns ( 57.08 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.155 ns ( 42.92 % ) " "Info: Total interconnect delay = 1.155 ns ( 42.92 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.691 ns" { clock clock~clkctrl display[6]~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.691 ns" { clock clock~combout clock~clkctrl display[6]~reg0 } { 0.000ns 0.000ns 0.118ns 1.037ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "display.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/display/display.vhd" 15 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.905 ns + Longest register pin " "Info: + Longest register to pin delay is 3.905 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns display\[6\]~reg0 1 REG LCFF_X23_Y35_N3 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X23_Y35_N3; Fanout = 1; REG Node = 'display\[6\]~reg0'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { display[6]~reg0 } "NODE_NAME" } } { "display.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/display/display.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.087 ns) + CELL(2.818 ns) 3.905 ns display\[6\] 2 PIN PIN_J11 0 " "Info: 2: + IC(1.087 ns) + CELL(2.818 ns) = 3.905 ns; Loc. = PIN_J11; Fanout = 0; PIN Node = 'display\[6\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.905 ns" { display[6]~reg0 display[6] } "NODE_NAME" } } { "display.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/display/display.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.818 ns ( 72.16 % ) " "Info: Total cell delay = 2.818 ns ( 72.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.087 ns ( 27.84 % ) " "Info: Total interconnect delay = 1.087 ns ( 27.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.905 ns" { display[6]~reg0 display[6] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.905 ns" { display[6]~reg0 display[6] } { 0.000ns 1.087ns } { 0.000ns 2.818ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.691 ns" { clock clock~clkctrl display[6]~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.691 ns" { clock clock~combout clock~clkctrl display[6]~reg0 } { 0.000ns 0.000ns 0.118ns 1.037ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.905 ns" { display[6]~reg0 display[6] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.905 ns" { display[6]~reg0 display[6] } { 0.000ns 1.087ns } { 0.000ns 2.818ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "display\[2\]~reg0 qin\[0\] clock 0.222 ns register " "Info: th for register \"display\[2\]~reg0\" (data pin = \"qin\[0\]\", clock pin = \"clock\") is 0.222 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 2.691 ns + Longest register " "Info: + Longest clock path from clock \"clock\" to destination register is 2.691 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clock 1 CLK PIN_P2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clock'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "display.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/display/display.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns clock~clkctrl 2 COMB CLKCTRL_G3 12 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 12; COMB Node = 'clock~clkctrl'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.118 ns" { clock clock~clkctrl } "NODE_NAME" } } { "display.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/display/display.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.037 ns) + CELL(0.537 ns) 2.691 ns display\[2\]~reg0 3 REG LCFF_X23_Y35_N13 1 " "Info: 3: + IC(1.037 ns) + CELL(0.537 ns) = 2.691 ns; Loc. = LCFF_X23_Y35_N13; Fanout = 1; REG Node = 'display\[2\]~reg0'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.574 ns" { clock~clkctrl display[2]~reg0 } "NODE_NAME" } } { "display.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/display/display.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.08 % ) " "Info: Total cell delay = 1.536 ns ( 57.08 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.155 ns ( 42.92 % ) " "Info: Total interconnect delay = 1.155 ns ( 42.92 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.691 ns" { clock clock~clkctrl display[2]~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.691 ns" { clock clock~combout clock~clkctrl display[2]~reg0 } { 0.000ns 0.000ns 0.118ns 1.037ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.266 ns + " "Info: + Micro hold delay of destination is 0.266 ns" {  } { { "display.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/display/display.vhd" 15 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.735 ns - Shortest pin register " "Info: - Shortest pin to register delay is 2.735 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.979 ns) 0.979 ns qin\[0\] 1 PIN PIN_C13 7 " "Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_C13; Fanout = 7; PIN Node = 'qin\[0\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { qin[0] } "NODE_NAME" } } { "display.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/display/display.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.130 ns) + CELL(0.150 ns) 2.259 ns Mux4~26 2 COMB LCCOMB_X23_Y35_N26 1 " "Info: 2: + IC(1.130 ns) + CELL(0.150 ns) = 2.259 ns; Loc. = LCCOMB_X23_Y35_N26; Fanout = 1; COMB Node = 'Mux4~26'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.280 ns" { qin[0] Mux4~26 } "NODE_NAME" } } { "display.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/display/display.vhd" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.243 ns) + CELL(0.149 ns) 2.651 ns display~72 3 COMB LCCOMB_X23_Y35_N12 1 " "Info: 3: + IC(0.243 ns) + CELL(0.149 ns) = 2.651 ns; Loc. = LCCOMB_X23_Y35_N12; Fanout = 1; COMB Node = 'display~72'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.392 ns" { Mux4~26 display~72 } "NODE_NAME" } } { "display.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/display/display.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 2.735 ns display\[2\]~reg0 4 REG LCFF_X23_Y35_N13 1 " "Info: 4: + IC(0.000 ns) + CELL(0.084 ns) = 2.735 ns; Loc. = LCFF_X23_Y35_N13; Fanout = 1; REG Node = 'display\[2\]~reg0'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.084 ns" { display~72 display[2]~reg0 } "NODE_NAME" } } { "display.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/display/display.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.362 ns ( 49.80 % ) " "Info: Total cell delay = 1.362 ns ( 49.80 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.373 ns ( 50.20 % ) " "Info: Total interconnect delay = 1.373 ns ( 50.20 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.735 ns" { qin[0] Mux4~26 display~72 display[2]~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.735 ns" { qin[0] qin[0]~combout Mux4~26 display~72 display[2]~reg0 } { 0.000ns 0.000ns 1.130ns 0.243ns 0.000ns } { 0.000ns 0.979ns 0.150ns 0.149ns 0.084ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.691 ns" { clock clock~clkctrl display[2]~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.691 ns" { clock clock~combout clock~clkctrl display[2]~reg0 } { 0.000ns 0.000ns 0.118ns 1.037ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.735 ns" { qin[0] Mux4~26 display~72 display[2]~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.735 ns" { qin[0] qin[0]~combout Mux4~26 display~72 display[2]~reg0 } { 0.000ns 0.000ns 1.130ns 0.243ns 0.000ns } { 0.000ns 0.979ns 0.150ns 0.149ns 0.084ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}