traffic_controller.map.qmsg

实现交通灯控制器的vhdl编程

{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "frequency20Hz frequency20Hz:inst3 " "Info: Elaborating entity \"frequency20Hz\" for hierarchy \"frequency20Hz:inst3\"" {  } { { "traffic_controller.bdf" "inst3" { Schematic "E:/SOPClab/digital_system_design/traffic_controller/traffic_controller.bdf" { { 72 224 352 168 "inst3" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "display display:inst6 " "Info: Elaborating entity \"display\" for hierarchy \"display:inst6\"" {  } { { "traffic_controller.bdf" "inst6" { Schematic "E:/SOPClab/digital_system_design/traffic_controller/traffic_controller.bdf" { { 416 680 832 512 "inst6" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "fenwei fenwei:inst4 " "Info: Elaborating entity \"fenwei\" for hierarchy \"fenwei:inst4\"" {  } { { "traffic_controller.bdf" "inst4" { Schematic "E:/SOPClab/digital_system_design/traffic_controller/traffic_controller.bdf" { { 304 392 552 400 "inst4" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "fenwei:inst5\|numA\[2\] data_in GND " "Warning: Reduced register \"fenwei:inst5\|numA\[2\]\" with stuck data_in port to stuck value GND" {  } { { "fenwei/fenwei.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/fenwei/fenwei.vhd" 13 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "fenwei:inst5\|numA\[3\] data_in GND " "Warning: Reduced register \"fenwei:inst5\|numA\[3\]\" with stuck data_in port to stuck value GND" {  } { { "fenwei/fenwei.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/fenwei/fenwei.vhd" 13 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "fenwei:inst4\|numA\[2\] data_in GND " "Warning: Reduced register \"fenwei:inst4\|numA\[2\]\" with stuck data_in port to stuck value GND" {  } { { "fenwei/fenwei.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/fenwei/fenwei.vhd" 13 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "fenwei:inst4\|numA\[3\] data_in GND " "Warning: Reduced register \"fenwei:inst4\|numA\[3\]\" with stuck data_in port to stuck value GND" {  } { { "fenwei/fenwei.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/fenwei/fenwei.vhd" 13 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "display:inst1\|timeout\[0\] display:inst7\|timeout\[0\] " "Info: Duplicate register \"display:inst1\|timeout\[0\]\" merged to single register \"display:inst7\|timeout\[0\]\"" {  } { { "display/display.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/display/display.vhd" 15 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "display:inst6\|timeout\[0\] display:inst7\|timeout\[0\] " "Info: Duplicate register \"display:inst6\|timeout\[0\]\" merged to single register \"display:inst7\|timeout\[0\]\"" {  } { { "display/display.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/display/display.vhd" 15 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "display:inst8\|timeout\[0\] display:inst7\|timeout\[0\] " "Info: Duplicate register \"display:inst8\|timeout\[0\]\" merged to single register \"display:inst7\|timeout\[0\]\"" {  } { { "display/display.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/display/display.vhd" 15 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "display:inst1\|timeout\[1\] display:inst7\|timeout\[1\] " "Info: Duplicate register \"display:inst1\|timeout\[1\]\" merged to single register \"display:inst7\|timeout\[1\]\"" {  } { { "display/display.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/display/display.vhd" 15 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "display:inst6\|timeout\[1\] display:inst7\|timeout\[1\] " "Info: Duplicate register \"display:inst6\|timeout\[1\]\" merged to single register \"display:inst7\|timeout\[1\]\"" {  } { { "display/display.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/display/display.vhd" 15 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "display:inst8\|timeout\[1\] display:inst7\|timeout\[1\] " "Info: Duplicate register \"display:inst8\|timeout\[1\]\" merged to single register \"display:inst7\|timeout\[1\]\"" {  } { { "display/display.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/display/display.vhd" 15 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "display:inst1\|timeout\[2\] display:inst7\|timeout\[2\] " "Info: Duplicate register \"display:inst1\|timeout\[2\]\" merged to single register \"display:inst7\|timeout\[2\]\"" {  } { { "display/display.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/display/display.vhd" 15 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "display:inst6\|timeout\[2\] display:inst7\|timeout\[2\] " "Info: Duplicate register \"display:inst6\|timeout\[2\]\" merged to single register \"display:inst7\|timeout\[2\]\"" {  } { { "display/display.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/display/display.vhd" 15 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "display:inst8\|timeout\[2\] display:inst7\|timeout\[2\] " "Info: Duplicate register \"display:inst8\|timeout\[2\]\" merged to single register \"display:inst7\|timeout\[2\]\"" {  } { { "display/display.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/display/display.vhd" 15 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "display:inst1\|timeout\[3\] display:inst7\|timeout\[3\] " "Info: Duplicate register \"display:inst1\|timeout\[3\]\" merged to single register \"display:inst7\|timeout\[3\]\"" {  } { { "display/display.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/display/display.vhd" 15 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "display:inst6\|timeout\[3\] display:inst7\|timeout\[3\] " "Info: Duplicate register \"display:inst6\|timeout\[3\]\" merged to single register \"display:inst7\|timeout\[3\]\"" {  } { { "display/display.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/display/display.vhd" 15 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "display:inst8\|timeout\[3\] display:inst7\|timeout\[3\] " "Info: Duplicate register \"display:inst8\|timeout\[3\]\" merged to single register \"display:inst7\|timeout\[3\]\"" {  } { { "display/display.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/display/display.vhd" 15 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "display:inst1\|timeout\[4\] display:inst7\|timeout\[4\] " "Info: Duplicate register \"display:inst1\|timeout\[4\]\" merged to single register \"display:inst7\|timeout\[4\]\"" {  } { { "display/display.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/display/display.vhd" 15 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "display:inst6\|timeout\[4\] display:inst7\|timeout\[4\] " "Info: Duplicate register \"display:inst6\|timeout\[4\]\" merged to single register \"display:inst7\|timeout\[4\]\"" {  } { { "display/display.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/display/display.vhd" 15 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "display:inst8\|timeout\[4\] display:inst7\|timeout\[4\] " "Info: Duplicate register \"display:inst8\|timeout\[4\]\" merged to single register \"display:inst7\|timeout\[4\]\"" {  } { { "display/display.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/display/display.vhd" 15 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "display:inst7\|display\[3\] display:inst7\|display\[0\] " "Info: Duplicate register \"display:inst7\|display\[3\]\" merged to single register \"display:inst7\|display\[0\]\"" {  } { { "display/display.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/display/display.vhd" 15 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "display:inst1\|display\[1\] display:inst7\|display\[1\] " "Info: Duplicate register \"display:inst1\|display\[1\]\" merged to single register \"display:inst7\|display\[1\]\"" {  } { { "display/display.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/display/display.vhd" 15 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "display:inst1\|display\[3\] display:inst1\|display\[0\] " "Info: Duplicate register \"display:inst1\|display\[3\]\" merged to single register \"display:inst1\|display\[0\]\"" {  } { { "display/display.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/display/display.vhd" 15 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "185 " "Info: Implemented 185 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "3 " "Info: Implemented 3 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "34 " "Info: Implemented 34 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "148 " "Info: Implemented 148 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 5 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Oct 04 16:17:17 2008 " "Info: Processing ended: Sat Oct 04 16:17:17 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}