traffic_controller.map.qmsg

实现交通灯控制器的vhdl编程

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Oct 04 16:17:14 2008 " "Info: Processing started: Sat Oct 04 16:17:14 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off traffic_controller -c traffic_controller " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off traffic_controller -c traffic_controller" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "traffic_controller.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file traffic_controller.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 traffic_controller " "Info: Found entity 1: traffic_controller" {  } { { "traffic_controller.bdf" "" { Schematic "E:/SOPClab/digital_system_design/traffic_controller/traffic_controller.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "frequency20Hz/frequency20Hz.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file frequency20Hz/frequency20Hz.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 frequency20Hz-behav " "Info: Found design unit 1: frequency20Hz-behav" {  } { { "frequency20Hz/frequency20Hz.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/frequency20Hz/frequency20Hz.vhd" 8 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 frequency20Hz " "Info: Found entity 1: frequency20Hz" {  } { { "frequency20Hz/frequency20Hz.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/frequency20Hz/frequency20Hz.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "frequency1Hz/frequency1Hz.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file frequency1Hz/frequency1Hz.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 frequency1Hz-behav " "Info: Found design unit 1: frequency1Hz-behav" {  } { { "frequency1Hz/frequency1Hz.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/frequency1Hz/frequency1Hz.vhd" 8 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 frequency1Hz " "Info: Found entity 1: frequency1Hz" {  } { { "frequency1Hz/frequency1Hz.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/frequency1Hz/frequency1Hz.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "fenwei/fenwei.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file fenwei/fenwei.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 fenwei-behav " "Info: Found design unit 1: fenwei-behav" {  } { { "fenwei/fenwei.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/fenwei/fenwei.vhd" 9 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 fenwei " "Info: Found entity 1: fenwei" {  } { { "fenwei/fenwei.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/fenwei/fenwei.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "display/display.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file display/display.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 display-behav " "Info: Found design unit 1: display-behav" {  } { { "display/display.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/display/display.vhd" 10 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 display " "Info: Found entity 1: display" {  } { { "display/display.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/display/display.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "controller/controller.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file controller/controller.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 controller-behav " "Info: Found design unit 1: controller-behav" {  } { { "controller/controller.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/controller/controller.vhd" 13 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 controller " "Info: Found entity 1: controller" {  } { { "controller/controller.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/controller/controller.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "traffic_controller " "Info: Elaborating entity \"traffic_controller\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "controller controller:inst " "Info: Elaborating entity \"controller\" for hierarchy \"controller:inst\"" {  } { { "traffic_controller.bdf" "inst" { Schematic "E:/SOPClab/digital_system_design/traffic_controller/traffic_controller.bdf" { { 72 600 736 264 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "reset controller.vhd(19) " "Warning (10492): VHDL Process Statement warning at controller.vhd(19): signal \"reset\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "controller/controller.vhd" "" { Text "E:/SOPClab/digital_system_design/traffic_controller/controller/controller.vhd" 19 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "frequency1Hz frequency1Hz:inst2 " "Info: Elaborating entity \"frequency1Hz\" for hierarchy \"frequency1Hz:inst2\"" {  } { { "traffic_controller.bdf" "inst2" { Schematic "E:/SOPClab/digital_system_design/traffic_controller/traffic_controller.bdf" { { 72 400 528 168 "inst2" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}